Verification of memory operations by multiple processors to...

Details Verification of memory operations by multiple processors to... Verification of memory operations by multiple processors to...

2007-04-03

2007-04-03

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S129000, C711S153000

Reexamination Certificate

active

10268238

ABSTRACT:
A method and apparatus for testing cache coherency in a multiprocessor data processing arrangement. Selected values are written to memory by a plurality of threads, and consistency of the values in the memory with the values written by the plurality of threads is verified. Performance characteristics of the data processing system are measured while writing the values, and in response to the performance characteristics relative to target performance characteristics, parameters that control writing by the plurality of threads are selectively adjusted.

REFERENCES:
patent: 6301616 (2001-10-01), Pal et al.
patent: 6430648 (2002-08-01), Carnevale
patent: 6535905 (2003-03-01), Kalafatis et al.
patent: 6889159 (2005-05-01), Klotz et al.

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