Verification of integrated circuit designs using buffer control

Details Verification of integrated circuit designs using buffer control Verification of integrated circuit designs using buffer control

2005-12-27

2005-12-27

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

06981238

ABSTRACT:
In one embodiment, a schematic for a net includes a load and a load schematic. The load schematic may include a parasitic on the net, and an equivalent of the load. A buffer may be employed to couple the load schematic to the schematic. Among other advantages, this simplifies comparison of parasitics between the schematic and a corresponding layout.

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Dimitri Doukas, et al., “CLOVER: A Timing Constraints Verification System”; 1991 ACM/IEEE Design Automation Conference, pp. 662-667; Dept. of Computer Science, Princeton Univ., New Jersey.

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