Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-03-06
2010-06-15
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C703S014000, C703S015000, C703S022000
Reexamination Certificate
active
07739633
ABSTRACT:
Testing a model of a logic circuit model. The testing includes generating valid random input stimulus sequences for a logic circuit model. Enumerating critical resource requirements, enumerating critical resource availabilities does this, and selecting of stimulus sequences and determining legal times for execution of said stimulus sequences based on resource availability. This includes generating a plurality of possible combinations of input stimulus sequences and generating an array representation of critical resource requirements. These are used to generate an array representation of critical resources availabilities.
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Ranaweera et al.; “Scheduling of periodic time critical applications for pipelined execution on heterogeneous systems”; Sep. 3-7, 2001; Parallel Processing, International Conference on, 2001; pp. 131-138.
P. Fay, E. Cerny, P. Pownall, “Improved Design Verification by Random Simulation Guided by Genetic Algorithms” (May 25, 2000).
Jorg Walter, Jena Leenstra, Gerhard Dottling, Bernd Leppla, Hans-Jurgen Muster, Kevin Karke, Bruce Wile, “Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors” (1997).
Ahmad Faisal A.
Gower Kevin C.
Patel Anish T.
Augspurger Lynn
Campbell John E.
International Business Machines - Corporation
Rossoshek Helen
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