Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-03-29
2004-08-31
Nguyen, T (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S146000, C711S155000, C714S037000, C714S047300, C714S051000
Reexamination Certificate
active
06785773
ABSTRACT:
BACKGROUND
1. Field of the Present Invention
The present invention generally relates to the field of data processing systems and more particularly to the design verification of a multi-node NUMA system.
2. History of Related Art
Symmetric Multi-Processing (SMP) architectures are widely used in the design of data processing systems such as computing servers. SMP servers are characterized by multiple processors that communicate with a common system memory across a shared bus. The limited bandwidth of the shared bus constrains the number of processors that can be deployed economically in an SMP machine and suggests the use of alternative technologies for building massively scaleable servers. In addition, standard high-volume, bus-based SMP servers are beginning to appear on the market thereby making it economically attractive to construct larger systems out of multiple standard nodes without fundamentally re-engineering the component machines.
One technology for constructing scaleable server machines is the Cache-Coherent, Non-Uniform Memory (ccNUMA) architecture, in which a special memory controller and a high-speed interconnection switch connect several SMP-based servers, which are referred to as nodes. A processor in this architecture accesses the local memory within its SMP node through its shared memory bus and accesses the remote memory residing on others nodes through the high-speed interconnect. Thus, local memory accesses are faster than remote memory accesses. The special memory controller typically uses a directory structure to ensure that all processors see shared memory accesses in a consistent and coherent manner. The result is a shared-memory architecture that does not have the limitations of a single memory bus, yet maintains the familiar shared-memory programming model.
Although NUMA systems may use SMP systems as a building block, verification of NUMA systems and, more particularly, coherency verification of a NUMA system is not readily accomplished use conventional SMP design verification tools. In a typical SMP design process, a proposed architecture is simulated using a software simulation tool. The simulation tool outputs files, referred to as event traces, which indicate the behavior of a proposed system. The event trace files may then be checked against a predetermined set of system checks to verify the coherency model. An SMP system has multiple processors that share a system memory via a common bus (the system bus). In an SMP system, the system bus provides a point of ordering for all transactions (i.e., the order is established by when the transactions occur on the shared bus) and coherency is enforced using a standard SMP coherency protocol such as MESI. Existing methods of verifying coherency in an SMP system rely on this SMP characteristic. See, e.g., Barrett, Jr., et al.,
Method and System for Testing a Multiprocessor Data Processing System
, U.S. Pat. No. 6,021,261 (Feb. 1, 2000).
In a NUMA system, there is no single point of ordering for the entire system. Instead, each node is associated with a range of addresses and the point of ordering for a specific transaction depends upon the range in which the address associated with a specific transaction lies. To account for this additional level of complexity, NUMA systems require a second coherency protocol (NUMA protocol) to enforce coherency across nodes. Unfortunately, existing methods of verifying coherency in an SMP system do not verify that the NUMA protocol is operating correctly and cannot therefore be used directly to verify coherence in a NUMA system. It would therefore be desirable to implement a method and system for verifying the coherence in a NUMA system. It would be further desirable if the implemented solution did not require substantial modification of existing verification software.
SUMMARY OF THE INVENTION
The problems identified above are in large part addressed by a system and method for verifying cache coherency in a multi-node, NUMA system. The system includes a transaction modification unit configured to receive event traces generated by a simulation tool. The transaction modification unit is designed to modify transactions that are propagated to another node in the NUMA system and thus result in two bus transactions, a home node transaction (HNT) and a foreign node transaction (FNT). More specifically, the modification unit merges a FNT and its corresponding HNT into a single merge transaction (MT) under a prescribed set of merging rules. The MT has properties of the both the FNT and the HNT. The FNT and HNT are deleted from the event trace and replaced by their corresponding MT to create a modified event trace that is suitable for coherency checking by a single system coherency checker. The merged transaction may include the event start and source of the originating transaction (the FNT) and the response, response time, and event stop of the resulting transaction (the HNT). The transactions subject to modification include non-ownership read transactions, ownership transactions, and write transactions that reference a memory address located on a different node. Non-ownership, foreign-node read transactions are modified if the corresponding cache line is invalid in all caches on the originating node. Foreign-node ownership transactions are modified if the corresponding cache line is not uniquely owned by a cache on the originating node. Foreign-node write transactions are always modified. In addition, invalidate transactions that are related to the NUMA protocol deleted from the modified event trace.
REFERENCES:
patent: 5996050 (1999-11-01), Carter et al.
patent: 6021261 (2000-02-01), Barrett et al.
patent: 6038651 (2000-03-01), VanHuben et al.
patent: 6324612 (2001-11-01), Chen et al.
patent: 6430646 (2002-08-01), Thusoo et al.
patent: 6658652 (2003-12-01), Alexander et al.
Farago Steven Robert
Leu Liang-Haw
McConville Lawrence Allyn
Wright Kenneth Lee
International Business Machines - Corporation
Lally Joseph P.
McBurney Mark E.
Nguyen T
LandOfFree
Verification of global coherence in a multi-node NUMA system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Verification of global coherence in a multi-node NUMA system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Verification of global coherence in a multi-node NUMA system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3285623