Verification of digital circuitry using range generators

Details Verification of digital circuitry using range generators Verification of digital circuitry using range generators

2006-10-03

2006-10-03

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07117463

ABSTRACT:
An embodiment of the present invention includes a range generator to simplify equivalence checking. A range generator is constructed. The range generator is represented by a characteristic function of a range of a cut function for a cut circuit in an implementation circuit and a reference circuit. The range generator is simpler than the cut circuit. Equivalence of the implementation circuit and the reference circuit is checked using the range generator.

REFERENCES:
Andreas Kuehlmann, et.al., Equivalence Checking Using Cuts and Heaps, ACM, IBM Thomas J. Watson Research Center, Yorktown Heights, NY.
Evgueni I. Goldberg, et. al., Using SAT for Combinational Equivalence Checking, University of Berkeley.
Henrik Hulgaard, et. al., Equivalence Checking of Combinational Circuits using Boolean Expression Diagrams, IEEE Transactions on CAD, Jul. 1999.
Chung-Yang (RIC) Huang, et. al., Static Property Checking Using ATPG v.s. BDD Techniques, University of California Santa Barbara, CA.
Alan Mishchenko, BDDs and Their Applications, www.ee.pdx.edu/˜alanmi/510FM2/510OCE-16.pdf, May 2000.
Congguang Yang, et. al., BDS: A BDD-Based Logic Optimization System, Uiversity of Massachusetts, Dept of Electrical & Computer Engineering, ACM, 2000, DAC.
Navin Vemuri, et. al., BDD-based Logic Synthesis for LUT-based FPGAs, ACM, 2002, Association for Computing Machinery.
Randal E. Bryant, Ordered Binary Decision Diagrams BDD, IEEE Transactions on Computers, vol. C-35, No. 8, 1986.
Sandeep K. Shukla, An Introduction to Formal Verification, CECS/ICS/University of California, Irvine.
R. P. Kurshan, Formal Verification in a Commercial Setting, The Verification Times, Bell Laboratories, 1997, Association for Computing Machinery, Inc.
Kurt Keutzer, Professor, Implementation Verification: Static Timing Verification, University of California Berkeley, CA.
Jim Smith, et. al., Polynomial Methods for Allocating Complex Components, Computer Systems Laboratory, Stanford University.
Wolfgang Kunz, Verification Problems and Solutions, Dept. of Computer Science, University of Frankfurt/Main, Germany.
Shi-Yu Huang, Formal Equivalence Checking And Design Debugging, 1998, Chapters 3-4, Kluwer Academic Publishers, Norwell, Massachusetts, USA.

Affiliated with

Also associated with

Rating

Verification of digital circuitry using range generators does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Verification of digital circuitry using range generators, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Verification of digital circuitry using range generators will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3618052