Vented CMOS dynamic logic system

Details Vented CMOS dynamic logic system Vented CMOS dynamic logic system

2000-09-07

2002-07-16

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S095000, C326S096000, C326S112000

Reexamination Certificate

active

06420905

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to data processing systems and in particular, CMOS dynamic logic circuitry.
BACKGROUND INFORMATION
A logic circuit is a circuit designed to perform a particular logical function based on the concepts of “and,” “not”, “either-or,” “neither-nor,” etc. Normally these circuits operate between two discreet voltage levels, a logic one and logic zero, and are described as binary logic circuits.
Binary logic circuits are the basic building blocks of data processing systems and almost any electronic computing device. Binary logic circuits are extensively used in computers to carry out instructions and arithmetic processes as well as store information. Any logical procedure may be realized by using a suitable combination of these basic gates.
Because of their lower power dissipation, complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) are often used to construct such logic circuits, but are by no means the only implementation of such logic circuits.
Logic circuits are often cascaded in a number of connected stages and clock pulses are applied to the logic circuits to synchronize logic operations.
FIG. 1
illustrates a logic circuit
100
which may implement a logic function having inputs Data In
101
and an output Data Out
102
. A Clock
103
may be used as a means to synchronize or time when the particular states on the inputs of Data In
101
are to be evaluated by the logic gates in logic circuit
100
and outputted as Data Out
102
. Other logic functions (not shown) may be static in nature and use no clocking scheme to synchronize operations. Rather, these logic functions operate to generate a combinatorial result based on inputs and the logic structure.
Although clocks are used to synchronize logic circuits, outputs are usually deemed valid until changed or updated by a subsequent clock state. Registers and latches are logic circuits that are typically clocked to enable outputs to be presented to succeeding circuits while remaining isolated from changing inputs until a clock state updates the contents.
There is another class of logic sometimes referred to as dynamic logic where gates have “valid” outputs during only one of the two logic states of a clock. During the second state of the clock, all of the logic gates are “pre-charged” to a specific voltage level. During the valid or first clock state, the logic gates “evaluate” or transition to the output states determined by inputs and the particular logic gate connections and structure. Dynamic logic is typically implemented with statically latched boundaries so that the outputs generated during an evaluation phase are not lost during a subsequent pre-charge phase.
Presently dynamic logic is used primarily to achieve an overall improvement in computation speed within processors. Paralleling logic circuits and pipelining various logic functions are techniques currently used to increase system speed. Dynamic logic is particularly suited to pipelined logic functions. In pipelined logic, a block of gates is used to determine a result which is then passed along to another block or stage of gates for further computation in a serial stream, called a “pipeline”.
Dynamic logic, in this disclosure, is differentiated from traditional clocked logic. The dynamic logic, referred to in this disclosure, shares the features of the previously discussed pre-charge and evaluate phases. There are many varieties of dynamic logic that are in the prior art and they are all driven by a clock or clocks. A partial list of these are: CMOS Domino Logic, NP Domino Logic, Cascade Voltage Switch Logic, and PE Logic. A reference,
Principles of CMOS VLSI Design. A Systems Perspective,
by Neil H. Weste and Kamran Eshraghian, Addison Wesley Pub. Co., discusses dynamic logic.
It is usually desirable for a binary circuit to run as fast as possible. The ultimate speed of any binary logic circuit is fundamentally limited by the switching speed of individual logic gates in the circuit. The switching speed of individual logic gates is, in turn, limited by the amount of charge that must be transferred to change logic states as well as the maximum rate in which the charge transfer can be accomplished, i.e., the maximum current.
For the purposes of understanding the switching speed limitations of CMOS logic, refer to
FIG. 2A
, which is a schematic of a static CMOS binary circuit consisting of two inverters in series. The first inverter consists of a P-channel FET (PFET)
200
and N-channel FET (NFET)
204
and the second inverter consists of PFET
203
and NFET
206
. The inverters are coupled creating a node Link
205
. The timing diagram in
FIG. 2B
illustrates waveforms
207
,
208
, and
209
for the voltages at each of the nodes (Data In
201
, Link
205
and Data Out
202
) as the input voltage (Data In
201
) on the first inverter transitions from a low to high voltage. Once the input Data In
201
supplies charge sufficient to establish a voltage greater than the threshold voltage (Vth
1
) of the NFET
204
, it becomes conductive and the charge stored in the capacitance of node Link
205
is removed to ground. If the previous voltage level on node Link
205
was Vdd (power supply voltage) then additional charge is removed by NFET
204
to charge the capacitance between the gate of PFET
203
and Vdd. When the threshold voltage (Vth
2
) of PFET
203
is exceeded, then it conducts and begins charging the output node Data Out
202
. This rather simple circuit illustrates the adding and removing of charge from nodes which is necessary for the operation of CMOS circuits. The FET devices charge and discharge the gate capacitances of the subsequent FETS. The time required for the gates to reach a voltage level is determined by the charge rate and the capacitances.
In a logic function comprising a group of logic gates with a set of inputs, not all of the gates will necessarily change from a present state when the set of inputs change logic states. The logic gates that do not change states require no time to generate their output since no transfer of charge is necessary to reach a valid state. If the logic gates in the logic function are dynamic with a pre-charge phase, the logic gates that remain in their pre-charged state during an evaluation will also require no time to generate their output since again no transfer of charge is necessary to reach a valid state. Although pre-charge will result in some gates having a minimum computation time, some gates will still require the time necessary to completely change states. In this sense conventional dynamic logic is asymmetrical; some gates make a full transition and some gates do not transition at all. It should be evident that even though some of the dynamic logic gates may have improved speed, it is never known how many gates will remain pre-charged or how many will change for a sequence of inputs. For this reason careful logic path selection and other techniques may be required to estimate and maximize the speed of a dynamic logic function.
Because speed in modem processors is very important, there is a need for selected dynamic logic functions with parallel computation paths and pipelined function architecture. There is therefore also a need for a dynamic logic that has a symmetrical operation resulting in faster logic gates with predictable and symmetrical gate switching times.
SUMMARY OF THE INVENTION
The present invention enables a logic circuit to run at a higher clock speed by minimizing the energy required for charge movement during evaluation. This is accomplished by causing the gate to transition to an intermediate voltage level during a pre-charge phase, henceforth referred to as “venting”. The venting may be implemented in a variety of ways, but in general, a venting circuit is enabled by a clock (vent clock) which reduces a node charge resulting in a node voltage between a high and a low logic level, typically the mid-point.
In one embodiment of the present invention, each input node of an inverting complementary metal oxi

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