Electrical computers and digital data processing systems: input/ – Interrupt processing – Multimode interrupt processing
Reexamination Certificate
2006-10-03
2006-10-03
Myers, Paul R. (Department: 2112)
Electrical computers and digital data processing systems: input/
Interrupt processing
Multimode interrupt processing
C711S162000
Reexamination Certificate
active
07117284
ABSTRACT:
A data processing apparatus is operable in a plurality of modes and in either a secure domain or a non-secure domain. When operating in a secure mode within the secure domain a program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A vectored interrupt controller is provided to generate an exception handler address in response to an occurrence of an except condition. The vectored interrupt controller is programmable with parameters specifying for each exception condition whether an exception handler in the secure or the non-secure domain should be triggered and an exception handler address for use if the exception occurs when in the appropriate domain. The vectored interrupt controller also includes a parameter specifying a domain switching exception handler address for use if the exception condition occurs when the processor is not in the appropriate domain.
REFERENCES:
patent: 5003466 (1991-03-01), Schan, Jr. et al.
patent: 5155853 (1992-10-01), Mitsuhira et al.
patent: 5596755 (1997-01-01), Pletcher et al.
patent: 5671422 (1997-09-01), Datta
patent: 5684948 (1997-11-01), Johnson et al.
patent: 5734910 (1998-03-01), Corrigan et al.
patent: 6003129 (1999-12-01), Song et al.
patent: 6240493 (2001-05-01), Hardwood et al.
patent: 6604123 (2003-08-01), Bruno et al.
patent: 6889279 (2005-05-01), Godfrey
patent: 2003/0101322 (2003-05-01), Gardner
patent: 2003/0140205 (2003-07-01), Dahan et al.
patent: 2004/0064351 (2004-04-01), Mikurak
patent: 1 054 322 (2000-11-01), None
patent: 1 162 536 (2001-12-01), None
patent: WO 99/38073 (1999-07-01), None
Trusted Computing Group (TCG), Main Specification Version 1.1a, Sep. 1, 2001, pp. i-x and 1-322.
Related U.S. Appl. No. 10/714,518.
Related U.S. Appl. No. 10/714,563.
Related U.S. Appl. No. 10/714,519.
Related U.S. Appl. No. 10/714,565.
Related U.S. Appl. No. 10/714,521.
Related U.S. Appl. No. 10/714,561.
Related U.S. Appl. No. 10/714,520.
Related U.S. Appl. No. 10/714,483.
Related U.S. Appl. No. 10/714,178.
Related U.S. Appl. No. 10/714,480.
Related U.S. Appl. No. 10/714,560.
Related U.S. Appl. No. 10/714,516.
Related U.S. Appl. No. 10/714,482.
Related U.S. Appl. No. 10/714,484.
Related U.S. Appl. No. 10/713,454.
Related U.S. Appl. No. 10/713,303.
Related U.S. Appl. No. 10/713,456.
Related U.S. Appl. No. 10/714,481.
Belnet Lionel
Brochier Stephane Eric Sebastien
Callan Jonathan Sean
Chaussade Nicolas
Dornan Christopher Bentley
ARM Limited
Myers Paul R.
Nixon & Vanderhye P.C.
LandOfFree
Vectored interrupt control within a system having a secure... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Vectored interrupt control within a system having a secure..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vectored interrupt control within a system having a secure... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3656285