Vector technique for addressing helper instruction groups...

Details Vector technique for addressing helper instruction groups... Vector technique for addressing helper instruction groups...

2007-05-15

2007-05-15

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S243000, C712S230000, C711S219000

Reexamination Certificate

active

10403530

ABSTRACT:
The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply, integer-divide, move on integer registers, graphics, floating point calculations or the like) are expanded into helper instructions before execution (e.g., in the integer, floating point, graphics and memory units or the like). Such instructions are treated as complex instructions. The functionality of a complex instruction is shared among multiple helpers so that by executing the helpers representing the complex instruction, the functionality of complex instruction is achieved. The expansion of complex instructions into helper instructions reduces the amount of hardware and complexity involved in supporting these individual complex instructions in various units in the processor.

REFERENCES:
patent: 5438668 (1995-08-01), Coon et al.
patent: 5754812 (1998-05-01), Favor et al.
patent: 5768575 (1998-06-01), McFarland et al.
patent: 5796973 (1998-08-01), Witt et al.
patent: 5805850 (1998-09-01), Luick
patent: 5822555 (1998-10-01), Brown et al.
patent: 5875316 (1999-02-01), Panwar et al.
patent: 5900018 (1999-05-01), Lynch
patent: 6038657 (2000-03-01), Favor et al.
patent: 6098165 (2000-08-01), Panwar et al.
patent: 6112282 (2000-08-01), Lynch
patent: 6173385 (2001-01-01), Tuma et al.
patent: 6366998 (2002-04-01), Mohamed
patent: 6658561 (2003-12-01), Benayoun et al.
patent: 6738892 (2004-05-01), Coon et al.
patent: 6789186 (2004-09-01), Brockmann et al.
patent: 2003/0229771 (2003-12-01), Thimmannagari et al.
patent: 2003/0229772 (2003-12-01), Thimmannagari et al.
patent: 2004/0133432 (2004-07-01), Sugumar et al.
patent: 2004/0133766 (2004-07-01), Abraham et al.
patent: 2004/0133768 (2004-07-01), Thimmannagari et al.
patent: 2004/0148496 (2004-07-01), Thimmannagari et al.
patent: 2004/0193844 (2004-09-01), Thimmannagari et al.
patent: 2004/0193845 (2004-09-01), Thimmannagari et al.
patent: 2004/0215941 (2004-10-01), Thimmannagari et al.
Culler, David. “Hardware-Software Trade-offs in Synchronization and Data Layout”. Feb. 17, 1999. Obtained on the web from: http://www.cs.berkeley.edu/˜culler/cs258-s99/lec09.pdf.
Hamacher, Carl. Vranesic, Zvonko. Zaky, Safwat. “Computer Organization”. McGraw-Hill Book Company, 2nd edition. 1978. pp. 137-141, 146-158.
Sakakibara et al. “Scalable Parallel Memory Architecture with a Skew Scheme”. Proceedings of the 7th international conference on Supercomputing, 1993. pp. 157-166.
Kitchen, Andrew, “Class Notes Chapter 8,”Control Structures, 1994.
Weaver, D. L. and Germond, Tom, “The SPARC Architecture Manual Version 9,” SPARC International Inc., 1994. pp. 133-136, 152-153, 227-228, and 263.

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