Patent
1995-06-07
1997-08-19
Eng, David Y.
G06F 1300
Patent
active
056597061
ABSTRACT:
The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plurality of independent functional units operably connected to the scalar processor, a vector processor for operating on vector instructions, including a plurality of independent functional units operably connected to the vector processor, and an instruction control mechanism for fetching both the scalar and vector instructions from an instruction cache and controlling the operation of those instructions in both the scalar and vector processor. The instruction control mechanism is designed to enhance the performance of the scalar/vector processor by keeping a multiplicity of pipelines substantially filled with a minimum number of gaps.
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"Dynamic Instruction Scheduling and the Astronautics ZS-1," James E. Smith, Astronautics Corporation of America, Jul., 1989, pp. 21-35.
Beard Douglas R.
Blewett Richard G.
Lohman Jeffrey A.
Phelps Andrew E.
Silbey Alexander A.
Cray Research Inc.
Eng David Y.
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