Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-02-10
2009-06-02
Peugh, Brian R (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C712S002000
Reexamination Certificate
active
07543119
ABSTRACT:
A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with a vector processor, and the processors collectively share access to a plurality of memory interfaces coupled to Dynamic Random Access read/write Memories (DRAMs). In typical embodiments the vector processor operates as a slave to the scalar processors, executing computationally intensive Single Instruction Multiple Data (SIMD) codes in response to commands received from the scalar processors. The vector processor implements a vector processing Instruction Set Architecture (ISA) including machine state, instruction set, exception model, and memory model.
REFERENCES:
patent: 4710867 (1987-12-01), Watanabe
patent: 4794521 (1988-12-01), Ziegler et al.
patent: 4916652 (1990-04-01), Schwarz et al.
Hessel Richard Edward
Keltcher Chetana N.
Tuck Nathan Daniel
Van Dyke Korbin S.
Peugh Brian R
Rodeen-Dickert Charlotte
West Stuart J.
West & Associates A PC
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