Vector processing unit with reconfigurable data buffer

Details Vector processing unit with reconfigurable data buffer Vector processing unit with reconfigurable data buffer

1997-05-16

1999-03-09

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

3958006, 711202, 711212, 711220, G06F 15347, G06F 1204

Patent

active

058813020

ABSTRACT:
A vector processing unit includes data buffers between a storage and a vector processor. Each of the data buffers is divided into four virtual buffers. Each virtual buffer can store 16 words of data, each word having 8 bytes. Accordingly, one load data buffer can store four 8-byte vector data when the vector length is 16, and one 8-byte vector data when the vector length is 64. By compressing two 4-byte vector data into one 8-byte vector data, it is possible to store four 4-byte vector data when the vector length is 32, and 4-byte vector data when the vector length is 128.

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patent: 5513366 (1996-04-01), Agarwal et al.
patent: 5598574 (1997-01-01), Yoshinaga et al.

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