Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
2006-04-25
2006-04-25
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C712S022000
Reexamination Certificate
active
07036001
ABSTRACT:
A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.
REFERENCES:
patent: 6343356 (2002-01-01), Pechanek et al.
patent: 6366999 (2002-04-01), Drabenstott et al.
patent: 6530012 (2003-03-01), Wilson
patent: 6839728 (2005-01-01), Pitsianis et al.
patent: WO 99/21078 (1999-04-01), None
Search Report for GB 0126133.8 dated Apr. 2, 2003.
Bailey Neil
Barlow Stephen
Plowman David
Ramsdale Timothy
Swann Robert
Broadcom Corporation
McAndrews Held & Malloy
Treat William M.
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