Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1993-09-07
1995-04-18
Hudspeth, David R.
Electronic digital logic circuitry
Interface
Logic level shifting
326121, H03K 19094
Patent
active
054081475
ABSTRACT:
A circuit for translating logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail in which the potentials of the two high-potential rails are not equal. The translator of the present invention is utilized in the transition from a 3V-supplied circuit to a 5V-supplied circuit, or vice versa, without any static current I.sub.CCt and regardless of the power-up sequencing. The static current is eliminated by isolating the output of the first stage of the translator, which is at the first high-potential power rail level, from all transistors of the second stage that are tied directly to the second high-potential power rail. In the preferred embodiment of the invention the transistors of the second stage that are powered by the second high-potential power rail are PMOS transistors and the isolation is achieved by linking those PMOS transistors to the first stage through a series of controlling NMOS transistors. In that way, the PMOS transistors will be completely turned off when necessary so as to avoid any undesirable conduction paths occurring due to differences in the potentials of the two high-potential power rails.
REFERENCES:
patent: 5101125 (1992-03-01), Hara et al.
patent: 5115434 (1992-05-01), Aizaki
patent: 5136190 (1992-08-01), Chern et al.
patent: 5300832 (1994-04-01), Rogers
patent: 5317214 (1994-05-01), Lewis
patent: 5321324 (1994-06-01), Hardee et al.
Chapin Jay R.
Yarbrough Roy L.
Bohan Thomas L.
Caseiro Chris A.
Hudspeth David R.
National Semiconductor Corporation
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