Varying TEOS flow rate while forming intermetallic insulating la

Details Varying TEOS flow rate while forming intermetallic insulating la Varying TEOS flow rate while forming intermetallic insulating la

1996-03-04

1998-09-08

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

H01L 0000

Patent

active

058045090

ABSTRACT:
Method of forming intermetallic insulating layers in semiconductor devices are disclosed, which not only have superior adhesion and homogeneous step coverage but also prevent the generation of voids due to the penetration of moisture. According to the method, metal interconnects are, first formed on the semiconductor substrate. Thereafter, a first insulating layer is formed to a thickness capable of sufficiently filling the spaces between the metal interconnects by reacting Tetraethylorthosilicate(TEOS) gas of a predetermined flow rate with O.sub.3 gas of a predetermined density in a CVD furnace. Next, a second insulating layer of a predetermined thickness is formed on the first insulating layer using the same furnace but by changing only the flow rate of TEOS.

REFERENCES:
patent: 5051380 (1991-09-01), Maeda et al.
patent: 5271972 (1993-12-01), Kwok et al.

Affiliated with

Also associated with

Rating

Varying TEOS flow rate while forming intermetallic insulating la does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Varying TEOS flow rate while forming intermetallic insulating la, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Varying TEOS flow rate while forming intermetallic insulating la will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1281888