Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-03-20
2007-03-20
Chu, Gabriel L. (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S741000, C703S015000
Reexamination Certificate
active
10627333
ABSTRACT:
Various methods and apparatuses are described in which a software programming interface connects one or more functional checker components and one or more protocol checker components to an interconnect monitor component. A computer readable medium stores code for the one or more functional checker components for Intellectual Property (IP) cores, one or more protocol checker components, the interconnect monitor component, and the software programming interface. The monitor component has code to build data structures containing protocol data types requested by a checker component and code on where to deliver data based upon a particular type of data requested by the checker component.
REFERENCES:
patent: 5948089 (1999-09-01), Wingard et al.
patent: 6182183 (2001-01-01), Wingard et al.
patent: 6263302 (2001-07-01), Hellestrand et al.
patent: 6292765 (2001-09-01), Ho et al.
patent: 6298452 (2001-10-01), Hill
patent: 6678645 (2004-01-01), Rajsuman et al.
patent: 6918058 (2005-07-01), Miura et al.
patent: 2002/0138814 (2002-09-01), Katayama
Microsoft Press Computer Dictionary Third Edition, “object-oriented”, Microsoft Press, 1997, p. 337.
Heinkel et al., “An Approach for a Dynamic Generation/Validation System for the Functional Simulation Considering Timing Constraints”, 1996 IEEE.
Chauhan et al. “Verifying IP-Core based System-on-Chip Designs”, 1999 IEEE.
Abhik Roychoudhury et al., “Using formal techniques to Debug the AMBA System-on-Chip Bus Protocol”, School of Computing National University of Singapore, Singapore 117543, {abhik, tulika, karrisid}@ comp.nus.edu.sq, prior to filing date of this application, pp. 6 total.
Sonics™ SMART IP for Greater SOC Complexity Faster, Synapse 3220, “Synapse 3220™ SMART Interconnect IP™”, www.sonicsinc.com/sonics/products/synapse 3220, May 30, 2003, pp. 1-2.
Thomas Anderson, Co-Chair, VSIA Functional Verification DWG, “Verification Reuse for Embedded Virtual Components”, 0-IN Design Automation, VSI Alliance™, Mar. 4, 2002, pp. 1-23.
Tom Anderson, VP of Applications Engineering 0-In Design Automation, Inc., Co-Chair, VSIA Functional Verification DWG, tla@ 0-in.com, “Verification: Reuse It or Lose It”, 0-IN Design Automation, DesignCon 2002, pp. 1-48.
“Open Core Protocol Specification,” OCP International Partnership, Release 1.0, 2001.
Alexanian Herve Jacques
Ebert Jeffrey Allen
Staton Terrence Anthony
Blakely , Sokoloff, Taylor & Zafman LLP
Chu Gabriel L.
Sonics, Inc.
LandOfFree
Various methods and apparatuses for interfacing of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Various methods and apparatuses for interfacing of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Various methods and apparatuses for interfacing of a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3761420