Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-07-19
2002-07-09
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S275000
Reexamination Certificate
active
06417548
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the storage of information by altering the operational characteristics of a transistor within an array of memory transistors and, more particularly, to a read only memory (ROM).
2. Description of the Related Art
Difficulties are encountered when attempting to increase the storage density of mask ROMs following conventional strategies. Alignment during mask ROM programming is important to the proper storage of information within mask ROMS. Difficulties encountered in achieving precise alignment in a production environment makes it difficult to further reduce the size of the field effect transistors used in forming the mask ROM while still obtaining acceptable yields. Certain of the difficulties in reducing the size of mask ROMs are discussed as follows.
A portion of a mask ROM
10
is schematically illustrated in
FIG. 1
as including a parallel array of word lines WL and a parallel array of bit lines BL. Programming of the ROM
10
is performed by selecting the performance characteristics of the circuit elements located at the intersections between the word lines WL and the bit lines BL. In the illustrated ROM, field effect transistors (FETs) having a drain connected to a bit line BL and a gate connected to a word line WL are located at each of the intersections between the word lines and the bit lines. Information is stored by selecting the threshold voltages of the field effect transistors formed at each of the intersections. A logical zero may be stored at the intersection of WL
0
and BL
0
by causing the field effect transistor
12
to have a relatively low threshold voltage; a logical one may be stored at the intersection
14
of word line WL
0
and bit line BL
1
by causing the FET at that location to have a relatively high threshold voltage.
Data read operations consist of applying a potential to both the word line and the bit line associated with a particular intersection or memory location, and may measure the potential on the bit line to determine if the transistor has a low threshold voltage. For example, if a low threshold voltage FET is present at the selected memory location, the potential applied to the gate of the selected FET drains the charge from the bit line, reducing the potential on the bit line to a level that is read as a logical zero. In this example, if a high threshold voltage FET is present at the selected intersection, the potential applied to the gate will not render the FET conductive so that the potential on the corresponding bit line will remain high and the data bit read out will be a logical one. ROMs may alternately perform the data read operation as a comparison between the bit line voltage and a reference voltage or the ROMs may perform the data read operation as a comparison of the threshold characteristics of the memory transistor against one or more reference transistors having selected threshold voltage characteristics.
FIG. 2
illustrates a conventional configuration of a portion of the
FIG. 1
ROM. The bit lines may be a parallel array of “buried” lines
22
,
24
,
26
and
28
formed as N
+
implantations into a P-type silicon substrate
20
. Lines
22
and
26
are connected to a potential source V and lines
24
and
28
are connected to a lower potential source, such as ground, so that lines
22
and
26
are FET drains and lines
24
and
28
are the sources of the FETs formed to store data in the illustrated ROM. A second array of conductive lines WL
0
, WL
1
, etc., is formed from, for example, a layer of doped polysilicon deposited on an insulation layer formed over the buried NE lines
22
,
24
,
26
and
28
. The conductive lines WL
0
, WL
1
, etc., are formed perpendicular to the implanted buried N
+
bit lines and will form the gates of the FETs of the ROM. To form lower threshold voltage transistors at selected ones
30
of the potential transistor positions and to form relatively high threshold voltage transistors at the other potential transistor positions
32
, processing differences must be introduced between the regions
30
and
32
.
FIG. 3
illustrates one conventional method of causing lower threshold voltage transistors to be formed at certain locations
30
(logical zeros) while forming relative high threshold voltage transistors at other locations
32
(logical ones). In
FIG. 3
, buried bit lines
22
,
24
,
26
and
28
form the sources and drains of the memory FETs, oxide layer
40
forms the gate insulator for the FETs, and word line WL
1
is the gate for the FETs. For those positions
30
at which a lower threshold voltage transistor is to be formed, the insulation layer
42
formed between the adjacent bit line implantations is made thin. Thus, insulation layer
42
is silicon oxide formed to a conventional gate oxide thickness. For those positions
32
at which a relatively high threshold voltage transistor is to be formed, the insulation layer
44
between adjacent bit line implantations is made sufficiently thick that the FET consisting of source and drain regions
24
and
26
, insulator
44
and gate WL
1
has a measurably higher threshold voltage. Accordingly, programming for the
FIG. 3
type of FET is accomplished by forming thick insulating films over the channel regions where high threshold voltage FETs are to be formed and growing thin insulator films over those FET channel regions where lower threshold voltage FETs are to be formed. Programming the
FIG. 3
mask ROM typically requires the formation of a mask which exposes those potential channel regions at which thick oxides are to be formed, growth of a thick oxide, removal of the mask, and growth of thinner gate oxides over those locations at which FETs are to be formed. This programming technique relies on the precise alignment of the mask with respect to the implantations to ensure that the thin oxide layer completely covers the channel regions at the appropriate positions. Misalignment in any direction can alter the characterization of desired FETs or form FETs where none were to be formed. In addition, it is difficult to form sufficiently thick insulating films for small cell sizes, so that it is difficult to increase the cell density using this programming technique. As such, it is increasingly difficult to implement this programming technique for smaller design rules.
FIG. 4
illustrates a second method for selecting the threshold voltage characteristics of the transistors to program the ROM illustrated in
FIGS. 1 and 2
. The
FIG. 4
ROM has a uniformly thin insulation layer over all of the channel regions of the FETs in the matrix. The threshold voltages of the FETs are selected by implanting different impurity levels into the channel regions of the transistors. For example, if the transistor would normally require a threshold adjust implant for acceptable operation, then programming of the ROM might consist of implanting an appropriate level of dopants into the channel regions of the FETs to be formed (logical zeros) and no implant is made into the channel regions of the FETs that are to have high threshold voltages (logical ones). If, on the other hand, no implant is necessary to enable the normal operation of a FET or if the difference between an unimplanted FET and a FET with a threshold adjust implant is too small to allow discrimination between implanted and unimplanted FETs, then an implant is made into the channels of those FETs that are not to be formed. Such an implant would be of a kind that increases the threshold voltage of the FET.
The processes for forming this ROM and for programming the ROM are now described. First, a mask is formed using photolithography on the substrate to expose the portions of the substrate into which dopants are implanted to define the buried N
+
layers. After the mask is removed, a uniform gate oxide is grown on the surface of the substrate, and then a layer of polysilicon is deposited over the gate oxide layer and the entire gate polysilicon layer is doped N-type with, for example, a
Kung Cheng-Chih
Sheu Shing-Ren
United Microelectronics Corp.
Weiss Howard
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