Electrical computers and digital processing systems: processing – Instruction alignment
Reexamination Certificate
2008-04-15
2008-04-15
Huisman, David J. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction alignment
C712S207000
Reexamination Certificate
active
07360059
ABSTRACT:
In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.
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Anderson William C.
Chalmers Kayla
Revilla Juan G.
Roth Charles P.
Singh Ravi P.
Analog Devices Inc.
Fish & Richardson P.C.
Huisman David J.
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