Variable voltage isolation gate and method

Details Variable voltage isolation gate and method Variable voltage isolation gate and method

2001-08-14

2002-09-03

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S205000, C365S189011

Reexamination Certificate

active

06445610

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor based memory devices, and in particular to sense amplifier isolation gates.
BACKGROUND OF THE INVENTION
Semiconductor memory devices contain memory cells for storing small electrical representative of bits of data. As storage densities are increasing, the cells, and circuitry used to access, sense and restore bits stored in the cells are becoming smaller and smaller. Sense amplifiers are used to detect and amplify the charges stored in the cells. As the size of the memory devices decrease, the charge to be detected decreases. In addition, the power supply voltages at which DRAMs operate are also decreasing to reduce the power consumption of the DRAMs. The lower power supply voltages, lead to slower circuit operations, or in some cases where transistors have relatively high threshold voltages, improper operation.
Isolation gates are used to connect digit lines coupled to multiple memory cells to sense amplifiers. In normal operation, the isolation gates selectively turned on and off during read, sense and restore cycles. First, the isolation gates are coupled to the power supply Vcc during initially accessing charges from a memory cell. In most cases, they are left on during sensing, but sometimes they have been turned off by coupling the gates to ground during sensing. Finally, the iso gates are coupled to Vcc during restore to turn them back on. As Vcc decreases, the threshold voltage, Vt, of the isolation gates becomes relatively large, and affects the ability of the sense amplifiers to sense the charge stored on the cells. The threshold voltage is not easily scalable. Further, high Vt relative to Vcc can affect the ability to restore the sensed cell due to significant resistance presented by the isolation gate. Some prior attempts to solve this problem on restore resumed in a pumped Vcc, Vccp, being applied to the isolation gates to reduce this resistance as seen in an IEEE paper entitled “Low Voltage High Speed Circuit Designs for Giga-bit DRAMs” by Lee et al., Symposium on VLSI Circuits Digest of Technical Papers, 1996, pp104,105.
There is a need for accurate reading of memory cells in DRAM devices. There is a further need for better detection of voltage differences on digit lines during access operation especially when the supply voltage of the DRAM is decreased. There is yet a further need for faster accessing, sensing and restoring of memory cells in DRAM devices.
SUMMARY OF THE INVENTION
A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage higher than the supply voltage during access time to ensure that a small differential voltage on the digit lines is correctly detected. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. In a further embodiment, during restore time, the isolation gate voltage is again raised above the supply voltage to minimize the effects of isolation transistor threshold voltage, Vt. This provides the ability to eliminate a Vt drop at access and restore times while providing better isolation of the digit lines when the sense amplifier fires.
In one embodiment, the voltage on the isolation gate is increased greater than Vt above Vcc at access time to Vccp, and then decreased during sense time to provide some amount of isolation from the digit lines. This provides for a faster driving of the isolated portions of the digit lines to Vcc and ground by the sense amplifiers.
In a further embodiment, the voltage on the isolation gate is increased to Vccp both during access time and during restore time to reduce adverse effects of Vt drops. In yet a further embodiment, the isolation gate voltage during access time is dropped below Vcc. In one embodiment, it is dropped to ground.
In yet a further embodiment, the voltage on the isolation gate is held at Vcc for both access and sense, and then increased to Vccp during restore time. A typical value for Vcc is 2.5 volts, and for Vccp is 4.0 volts. When Vt is almost 1 volt, and the digit or bit lines are equilibrated at 1.25 volts, Vt of the isolation gates adversely affects accurate sensing of the digit lines. Even further reductions in Vcc exacerbate the problem. By increasing the voltage of the isolation gates above Vcc at selected times, sensing accuracy is greatly improved, and restore operations are enhanced. In addition, reducing the isolation gate voltage during read time helps speed the driving of the sense amplifier lines to Vcc and ground by providing increased resistance or isolation between the sense amplifiers and the digit lines.


REFERENCES:
patent: 5301160 (1994-04-01), McAdams
patent: 5305261 (1994-04-01), Furutani et al.
patent: 5311478 (1994-05-01), Zagar et al.
patent: 5369620 (1994-11-01), Sugibayashi
patent: 5369622 (1994-11-01), McLaury
patent: 5418753 (1995-05-01), Seki
patent: 5444662 (1995-08-01), Tanaka et al.
patent: 5506811 (1996-04-01), McLaury
patent: 5553028 (1996-09-01), McLaury
patent: 5574681 (1996-11-01), Foss et al.
patent: 5612912 (1997-03-01), Gillingham
patent: 5623446 (1997-04-01), Hisada et al.
patent: 5822264 (1998-10-01), Tomishima et al.
patent: 5894444 (1999-04-01), Seyyedy
patent: 5901078 (1999-05-01), Porter et al.
patent: 0595747 (1994-05-01), None

Affiliated with

Also associated with

Rating

Variable voltage isolation gate and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Variable voltage isolation gate and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable voltage isolation gate and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2855177