Variable timing circuit

Details Variable timing circuit Variable timing circuit

2006-04-25

2006-04-25

Le, Don (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

C326S037000, C326S038000, C326S093000

Reexamination Certificate

active

07034577

ABSTRACT:
Systems and methods for delaying a signal by a selectable amount of time, wherein the selectable amount of time is adjustable in relatively small increments and wherein the variability of the selectable amounts of time is minimized. One embodiment comprises a circuit formed by a plurality of silicon-on-insulator (SOI) logic gates. The logic gates form a plurality of signal paths through the circuit, each of which imparts a corresponding delay to a signal routed through the path. Each of the signal paths includes a common portion formed by body-tied logic gates that imparts a fixed portion of the total signal delay, and a selectable portion formed by floating-body logic gates that imparts a selectable portion of the total signal delay. The circuit thereby reduces variations in the delay and also provides relatively small incremental changes in the selectable amount delay.

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Kang, Won-Gu et al: “A Novel Body-tied Silicon-On-Insulator (SOI) n-channel Metal-Oxide-Semiconductor Field-Effect-Transistor with Grounded Body Electrode” ETRI Journal vol. 7, No. 4, Jan. 1996.
Bernstein et al; SOI Circuit Design Concepts;SOI Timing Variability; Chapter 8.7; Kluwer Academic Publishers, no date.

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