Variable temperature methods of forming hemispherical...

Details Variable temperature methods of forming hemispherical... Variable temperature methods of forming hemispherical...

1998-01-26

2001-06-12

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S255000

Reexamination Certificate

active

06245632

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of microelectronics and more particularly to methods of forming hemispherical grained silicon layers.
BACKGROUND OF THE INVENTION
As integrated circuit memory devices become more highly integrated, the area of the substrate available for each memory cell is reduced. Accordingly, each memory cell capacitor and memory cell transistor must be fabricated on a smaller area of the substrate. By reducing the area available for the memory cell capacitor, however, it may be difficult to maintain a desired capacitance.
The capacitance C of a capacitor is proportional to the surface area A of the capacitor storage electrode and to the dielectric constant &egr; of the dielectric between the capacitor electrodes. The capacitance is inversely proportional to the distance d between the storage electrodes which is also the thickness of the dielectric layer. These relationships are mathematically shown in the following equation:
C=
&egr;(
A/d
).
Accordingly, memory devices having increased integration densities may have reduced memory cell capacitances.
A memory cell capacitor is used to store a bit of data in a dynamic random access memory device. In particular, the presence of a first predetermined electrical charge indicates a data value of “1”, and the presence of a second predetermined electrical charge indicates a data value of “0”. Accordingly, the capacitor should be capable of maintaining the predetermined charges without significant variations. In particular, charge variations (causing soft errors) due to external influences such as alpha-particles should be reduced. There is thus a need to maintain a predetermined capacitance for memory cell capacitors despite the reduced substrate areas available for each memory cell capacitor.
Methods for increasing the surface area of a capacitor electrode on a predetermined area of a substrate have thus been explored. In particular, capacitor storage electrodes have been developed having three-dimensional structures such as stack-type electrodes, cylindrical type electrodes, and fin type electrodes. The manufacturing steps used to produce these three-dimensional structures, however, may be undesirably complex.
Alternately, hemispherical grained silicon (HSG-Si) layers have been used to provide capacitor storage electrodes having increased surface areas. These structures can be formed with less complexity than may be required to form the above mentioned three-dimensional structures. A method for forming a hemispherical grained silicon layer will now be discussed with reference to FIG.
1
.
FIG. 1
is a graph illustrating the process temperatures for steps of a conventional method of forming a hemispherical grained silicon layer. As shown, this method includes three steps: a standby step
10
; a seeding step
12
; and an annealing step
14
. The standby step
10
is used to prepare a wafer used in the formation of the hemispherical grained silicon layer wherein the wafer is heated prior to forming the hemispherical grained silicon layer on the wafer. Before heating the wafer, a capacitor storage electrode is formed on the wafer.
During the seeding step
12
, HSG seeds are implanted on the capacitor storage electrode, and these HSG seeds provide nuclei for the formation of the hemispherical grained silicon layer. The seeding step
12
is performed at a temperature t
2
which is the same temperature used during the standby step
10
. During the annealing step
14
, silicon is grown from the seeds implanted on the wafer to form the hemispherical grained silicon layer. This annealing step is performed at a temperature t
1
which is lower than the temperature t
2
used during the standby step
10
and the seeding step
12
.
As discussed above, the standby step
10
and the seeding step
12
are performed at the same temperature when forming a hemispherical grained silicon layer according to the prior art. The capacitor storage electrode may thus be overheated during the standby step
10
thereby resulting in crystallization of the storage electrode. As a result, the quality of the HSG seeds formed during the seeding step
12
may be reduced. Accordingly, it may be difficult to form a stable hemispherical grained silicon layer during the annealing step
14
.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of forming hemispherical grained silicon layers.
It is another object of the present invention to provide capacitor storage electrodes having increased surface areas.
These and other objects are provided according to the present invention by methods including the steps of providing a microelectronic substrate, including a conductive layer thereon, and heating the conductive layer to a first predetermined temperature. Hemispherical grained silicon seeds are formed on the conductive layer while maintaining the conductive layer and the substrate at a second predetermined temperature higher than the first predetermined temperature. The hemispherical grained silicon seeds are annealed at a third predetermined temperature lower than the second predetermined temperature thereby growing the seeds to form a hemispherical grained silicon layer on the conductive layer. By heating the conductive layer to the first predetermined temperature lower than the second predetermined temperature, undesired crystallization of the conductive layer can be reduced, thereby increasing the uniformity of the hemispherical grained silicon layer formed thereon. Accordingly, the surface area of the hemispherical grained silicon layer can be increased.
The first and third temperatures can be approximately the same. Alternately, the first and third temperatures can be different as long as both are less than the second temperature. Moreover, the step of forming the hemispherical grained silicon seeds can include exposing the conductive layer to a silicon source gas such as silane or disilane.
The conductive layer can be an amorphous silicon layer. In addition, the step of heating the conductive layer can be preceded by the step of patterning the conductive layer so that portions of the substrate are exposed adjacent the patterned conductive layer. The method can also include the steps of forming a dielectric layer on the hemispherical grained silicon layer, and forming a second conductive layer on the dielectric layer.
According to the methods discussed above, a uniform hemispherical grained silicon layer can be formed on a capacitor storage electrode thereby increasing a surface area of the electrode. Accordingly, the capacitance of a resulting capacitor can be increased. A memory device including a capacitor as discussed above can thus provide more reliable operation.


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H. Watanabe et al., Hemispherical Grained Silicon (HSG-Si) Format

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