Variable stage entry/exit instruction pipeline

Details Variable stage entry/exit instruction pipeline Variable stage entry/exit instruction pipeline

1992-05-06

1995-11-28

Harvey, Jack B.

395375, G06F 938

Patent

active

054716268

ABSTRACT:
An instruction pipeline includes a sequence of interconnected pipeline stages, each stage dedicated to one of several operations executed on data in a digital processing device. Control words govern execution of the operations as they progress through the pipeline. The pipeline stages, as well as the pipeline entry and exit, are interconnected in a manner that permits each control word to enter and exit the pipeline at any one of the stages, and to skip any stages in which the control word will not govern any operations on data. On occasion, this permits a control word to bypass another control word which originally preceded it in the pipeline, thus to reverse the order of the two control words. A mapping field in each control word predetermines its route through the instruction pipeline, one bit of the map field corresponding to each pipeline stage. The route of each control word further is controlled by arbitration logic to resolve contentions among control words for particular pipeline stages, and to insure against a reversal in control word order when such reversal might produce an error. Each pipeline stage is a data register configured to accommodate one control word at a time. Succeeding stage registers are selectively reduced in length to eliminate selected segments and bit positions, thereby deleting from each control word certain bits and multiple bit fields executed in preceding stages.

REFERENCES:
patent: 4228497 (1980-10-01), Gupta et al.
patent: 4450525 (1984-05-01), Demuth et al.
patent: 4574344 (1986-03-01), Harris et al.
patent: 4722049 (1988-01-01), Lahti
patent: 4777594 (1988-10-01), Jones et al.
patent: 4855947 (1989-08-01), Zymslowski et al.
patent: 4890221 (1989-12-01), Gage
patent: 4893233 (1990-01-01), Denman et al.
patent: 5099421 (1992-03-01), Buerkle et al.
IBM Technical Disclosure Bulletin, vol. 34, No. 7A, Dec. 1991, pp. 472-480, "Data Processing System".
"Instruction Reorganization for a Variable-Length Pipelined Microprocessor", S. Abraham and K. Padmanabhan, International Conference on Computer Design, Oct. 3, 1988, New York, pp. 96-101.

Affiliated with

Also associated with

Rating

Variable stage entry/exit instruction pipeline does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Variable stage entry/exit instruction pipeline, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable stage entry/exit instruction pipeline will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2020985