Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2002-01-10
2004-03-23
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S026000, C326S027000
Reexamination Certificate
active
06710617
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to transmission lines in integrated circuits, and more particularly to a method and circuit for controlling the slew rate of a transitioning signal on a node of integrated circuit using stepwise impedance reduction/augmentation.
BACKGROUND OF THE INVENTION
Integrated circuits provide communication using digital signals. In the digital world, a digital signal may be in one of a plurality of predefined quantized states. Because digital signals are transmitted using an analog signal along a transmission line, the predefined quantized states of the digital signal are represented by different ranges of voltages within the total voltage range of the signal. For example, a typical digital integrated circuit (IC) based on a binary system will communicate using two states—zero (“0”) or LOW, and one (“1”) or HIGH. The digital state of “0” is represented by the range of voltages between a minimum voltage V
MIN
(e.g., 0 volts) of the potential voltage range of the signal and a voltage V
LOW
that is low relative to the total range of voltage, whereas the digital state of “1” is represented by the range of voltages between a voltage V
HIGH
that is high relative to the total range of voltages and a maximum voltage V
MAX
(e.g., 1.5 volts) of the potential voltage range of the signal. In the binary system example, the state of the digital signal is unknown when the voltage level of the signal is between V
LOW
and V
HIGH
. This unknown state typically occurs only during transitions of the signal from either the “0” state to the “1” state or vice versa.
At the integrated circuit level, a signal trace takes on the characteristics of a transmission line. Because the transmission signal is actually analog, the transition between digital states does not occur instantaneously, but instead occurs over a period of time T
TRANSITION
that is dependent on the physical conditions present on the transmission line. It is well known that signal transitions over a transmission line will suffer a delay known as a propagation delay due to the parasitic resistance, inductance, and capacitance of the line. This delay increases with the length of the line. In addition, it is also well-known that unless the impedance of the transmission line matches that of the load it drives, the signal will degrade. Signal degradation of this type occurs because the mismatch in impedance causes reflections from the load that are passed back to the driver circuit. These reflections may then be re-reflected by the driver circuit, causing further signal degradation.
It is also known that when a driver circuit drives multiple loads with differing impedances, the transmission line requires multiple stubs to properly match each of the loads during realtime operation. However, the use of multiple stubs then generates multiple reflections.
One way of ensuring proper detection of signal states is to slow the slew rates of the signal. The slew rate is the slope at which the signal edges transition between non-floating states.
SUMMARY OF THE INVENTION
The present invention is a novel method and circuit for controlling the slope of a transitioning signal on a node of integrated circuit using stepwise impedance reduction/augmentation. The invention allows precise control over the slew rate of the signal, which thereby allows matching of the transition times on both the rising and falling edges of the signal. In accordance with the method of the invention, an open drain node displaying transmission line characteristics is pulled from a first state to a second state over a plurality of sequentially ordered steps. At each step, a predetermined decreasing (or increasing) impedance is connected between the node and a voltage source representing the second state. Preferably, the order of the predetermined impedances decrease (or increase) non-linearly such that said signal transition seen on the node results in a linear slew rate. When the output signal is to transition from the high state to the low state, the pulldown driver decreases the impedance between the node and voltage source in an ordered stepwise manner. When the output signal is to transition from the low state to the high state, the pulldown driver increases the impedance between the node and low voltage source in reverse order stepwise manner.
In accordance with one embodiment of the invention, a plurality of serially connected variable delay units generates a plurality of delayed versions of the data signal to be driven onto the transmission line. When the output signal is to be pulled to a given state, a predriver circuit programs a variable impedance network to connect a different one of a plurality of predetermined impedances in ascending or descending order between the node and a voltage source once for each delayed version of transitioned data signal. The shape of the transition edges may be precisely shaped through a combination of the selection of the number of steps, impedance values for each step, and time delay between each step. In one embodiment, the values of the predetermined impedances in order of their connection between the node and voltage source is non-linear to result in a linear slew rate of a resulting output signal on the node.
Preferably, the delay time between each step is equal so as to allow the slew rate to be adjusted without affecting the linearity of the slew rate. This also allows slew rate adjustment by a PVT control circuit to account for process, voltage, and temperature variations in the components of the integrated circuit.
REFERENCES:
patent: 5170073 (1992-12-01), Hahn et al.
patent: 5923183 (1999-07-01), Kim et al.
patent: 6281729 (2001-08-01), Ang et al.
patent: 6288563 (2001-09-01), Muljono et al.
patent: 6295572 (2001-09-01), Wu
patent: 6297677 (2001-10-01), Ang et al.
Agilent Technologie,s Inc.
Tran Anh
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