Variable sized soft memory macros in structured cell arrays,...

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S187000

Reexamination Certificate

active

07876601

ABSTRACT:
The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may have different requirements (e.g., in terms of size) for such memory blocks. For example, pre-designed macros of memory blocks may be provided and then combined as needed to provide memory blocks of various sizes. Placement constraints may be observed for certain portions of the memory circuitry (e.g., the memory core), while other portions (e.g., address predecoder circuitry, write and read data registers, etc.) may be located relatively freely.

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patent: 2007/0210827 (2007-09-01), Chua et al.

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