Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1998-11-24
2001-04-17
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S086000
Reexamination Certificate
active
06218857
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention is generally directed to integrated circuits, more specifically to Programmable Logic Devices (PLDs), and even more specifically to a subclass of PLDs known as Field Programmable Gate Arrays (FPGAs).
2a. Cross Reference to Related Applications
The following copending U.S. patent applications are assigned to the assignee of the present application, and their disclosures are incorporated herein by reference:
(A) Ser. No. 08/995,614 [Attorney Docket No. AMDI8237] filed Dec.22, 1997, by Om Agrawal et al. and originally entitled, “INPUT/OUTPUT BLOCK (IOB) CONNECTIONS TO MAXL LINES, NOR LINES AND DENDRITES IN FPGA INTEGRATED CIRCUITS”;
(B) Ser. No. 08/912,763 [Attorney Docket No. AMDI8195] filed Aug. 18, 1997, by Bradley A. Sharpe-Geisler and originally entitled, “OUTPUT BUFFER FOR MAKING A 2.5 VOLT CIRCUIT COMPATIBLE WITH A 5.0 VOLT CIRCUIT”;
(C) Ser. No. 08/948,306 [Attorney Docket No. AMDI8222] filed Oct. 9, 1997, by Om Agrawal et al. and originally entitled, “VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS”;
(D) Ser. No. 08/996,361 [Attorney Docket No. AMDI8223] filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “SYMMETRICAL, EXTENDED AND FAST DIRECT CONNECTIONS BETWEEN VARIABLE GRAIN BLOCKS IN FPGA INTEGRATED CIRCUITS”;
(E) Ser. No. 08/995,615 [Attorney Docket No. AMDI8236] filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “A PROGRAMMABLE INPUT/OUTPUT BLOCK (IOB) IN FPGA INTEGRATED CIRCUITS”;
(F) Ser. No. 08/995,612 [Attorney Docket No. AMDI8238] filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “FLEXIBLE DIRECT CONNECTIONS BETWEEN INPUT/OUTPUT BLOCKs (IOBs) AND VARIABLE GRAIN BLOCKs (VGBs) IN FPGA INTEGRATED CIRCUITS”;
(G) Ser. No. 08/997,221 [Attorney Docket No. AMDI8239] filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “PROGRAMMABLE CONTROL MULTIPLEXING FOR INPUT/OUTPUT BLOCKs (IOBs) IN FPGA INTEGRATED CIRCUITS”;
(H) Ser. No. 08/996,119 [Attorney Docket No. AMDI8263] filed Dec. 22, 1997, by Bradley Sharpe-Geisler and originally entitled, “MULTIPLE INPUT ZERO POWER AND/NOR GATE FOR USE WITH A FIELD PROGRAMMABLE GATE ARRAY (FPGA)”; and,
(I) Ser. No. 08/996,442 [Attorney Docket No. AMDI8267] filed Dec. 22, 1997, by Bradley Sharpe-Geisler and originally entitled, “INPUT BUFFER PROVIDING VIRTUAL HYSTERESIS”.
2b. Cross Reference to Related Patents
The following U.S. patents are assigned to the assignee of the present application, and their disclosures are incorporated herein by reference:
(A) U.S. Pat. No. 5,212,652, issued May 18, 1993 to Om Agrawal et al. and entitled, “PROGRAMMABLE GATE ARRAY WITH IMPROVED Inter-connect STRUCTURE”;
(B) U.S. Pat. No. 5,621,650, issued Apr. 15, 1997 to Om Agrawal et al. and entitled, “PROGRAMMABLE LOGIC DEVICE WITH INTERNAL TIME-CONSTANT MULTIPLEXING OF SIGNALS FROM EXTERNAL INTER-CONNECT BUSES”;
(C) U.S. Pat. No. 5,185,706, issued Feb. 9, 1993 to Om Agrawal et al. and entitled, “PROGRAMMABLE GATE ARRAY WITH LOGIC CELLS HAVING CONFIGURABLE OUTPUT ENABLE”; and
(D) U.S. Pat. No. 5,740,069, issued Apr. 14, 1998 to Om Agrawal et al. and entitled, “LOGIC DEVICE (PLD) HAVING DIRECT CONNECTIONS BETWEEN CONFIGURABLE LOGIC BLOCKS (CLBs) AND CONFIGURABLE INPUT/OUTPUT BLOCKS (IOBs)”.
3. Description of Related Art
Field-Programmable Logic Devices (FPLDs) have continuously evolved to better serve the unique needs of different end-users. From the time of introduction of simple PLDs such as the Advanced Micro Devices 22V10 Programmable Array Logic device (PAL), the art has branched out in several different directions.
One evolutionary branch of FPLDs has grown along a paradigm known as Complex PLDs or CPLDs. This paradigm is characterized by devices such as the Advanced Micro Devices MACH family. Examples of CPLD circuitry are seen in U.S. Pat. Nos. 5,015,884 (issued May 14, 1991 to Om P. Agrawal et al.) and U.S. Pat. No. 5,151,623 (issued Sep. 29, 1992 to Om P. Agrawal et al.).
Another evolutionary chain in the art of field programmable logic has branched out along a paradigm known as Field Programmable Gate Arrays or FPGAs. Examples of such devices include the XC2000 and XC3000 families of FPGA devices introduced by Xilinx, Inc. of San Jose, Calif. The architectures of these devices are exemplified in U.S. Patent Nos. 4,642,487; 4,706,216; 4,713,557; and 4,758,985; each of which is originally assigned to Xilinx, Inc.
An FPGA device can be characterized as an integrated circuit that has four major features as follows.
(1) A user-accessible, configuration-defining memory means, such as SRAM, EPROM, EEPROM, anti-fused, fused, or other, is provided in the FPGA device so as to be at least once-programmable by device users for defining user-provided configuration instructions. Static Random Access Memory or SRAM is of course, a form of reprogrammable memory that can be differently programmed many times. Electrically Erasable and reProgrammable ROM or EEPROM is an example of nonvolatile reprogrammable memory. The configuration-defining memory of an FPGA device can be formed of mixture of different kinds of memory elements if desired (e.g., SRAM and EEPROM).
(2) Input/Output Blocks (IOBs) are provided for inter-connecting other internal circuit components of the FPGA device with external circuitry. The IOBs' may have fixed configurations or they may be configurable in accordance with user-provided configuration instructions stored in the configuration-defining memory means.
(3) Configurable Logic Blocks (CLBs) are provided for carrying out user-programmed logic functions as defined by user-provided configuration instructions stored in the configuration-defining memory means. Typically, each of the many CLBs of an FPGA has at least one lookup table (LUT) that is user-configurable to define any desired truth table,—to the extent allowed by the address space of the LUT. Each CLB may have other resources such as LUT input signal pre-processing resources and LUT output signal post-processing resources. Although the term ‘CLB’ was adopted by early pioneers of FPGA technology, it is not uncommon to see other names being given to the repeated portion of the FPGA that carries out user-programmed logic functions. The term, ‘LAB’ is used for example in U.S. Pat. No. 5,260,611 to refer to a repeated unit having a 4-input LUT.
(4) An inter-connect network is provided for carrying signal traffic within the FPGA device between various CLBs and/or between various IOBs and/or between various IOBs and CLBS. At least part of the inter-connect network is typically configurable so as to allow for programmably-defined routing of signals between various CLBs and/or IOBs in accordance with user-defined routing instructions stored in the configuration-defining memory means. Another part of the interconnect network may be hard wired or nonconfigurable such that it does not allow for programmed definition of the path to be taken by respective signals traveling along such hard wired inter-connect. A version of hard wired interconnect wherein a given conductor is dedicatedly connected to be always driven by a particular output driver, is sometimes referred to as ‘direct connect’.
Typically, IOBs have a driving amplifier (or driver) for generating signals into the FPGA inter-connect network from the IOB. An IOB may have multiple amplifiers for driving different types of inter-connect lines in the inter-connect network. For example, a first amplifier may drive a direct connect line having a predetermined length to a CLB, while a second. amplifier may drive a much shorter or much longer line to another IOB. If an amplifier is not large enough to drive a relatively long line, signal propagation times may be unduly large. Similarly, if a relatively large amplifier is used to drive a relatively short line, resources are unnecessarily wasted and related circuitry is loaded down which reduces signal propagation time. Accordingly, an optimal driver size must be determined for each sit
Sharpe-Geisler Bradley A.
Tran Giap
Cho James H.
Fliesler Dubb Meyer & Lovejoy LLP
Tokar Michael
Vantis Corporation
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