Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2007-05-08
2007-05-08
Elmore, Reba I. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S103000, C711S118000, C711S165000
Reexamination Certificate
active
10443629
ABSTRACT:
A method and apparatus for allocating a variable amount of memory to a device coupled to a bus are disclosed. In one embodiment, a first register contains a first value. A second register (e.g., Base Address Register) contains a second value that represents a default amount of memory to allocate to the device. The second value is automatically altered to indicate an updated amount of memory to allocate based on the first value. The ability to alter the default memory value substantially eliminates memory holes, which are unused portions of memory that have been allocated to devices coupled to the bus.
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patent: 5657455 (1997-08-01), Gates et al.
patent: 5881281 (1999-03-01), Gates et al.
patent: 6220510 (2001-04-01), Everett et al.
patent: 6327194 (2001-12-01), Kurihara et al.
patent: 6775423 (2004-08-01), Kulkarni et al.
Gilsdorf Kyle D.
Munguia Peter R.
Blakely , Sokoloff, Taylor & Zafman LLP
Elmore Reba I.
Intel Corporation
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