Variable-size first in first out memory with data manipulation c

Details Variable-size first in first out memory with data manipulation c Variable-size first in first out memory with data manipulation c

1994-11-04

1996-05-07

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Serial read/write

365231, 365238, G11C 700

Patent

active

055153291

ABSTRACT:
A FIFO memory system exhibits data processing capabilities by the inclusion therein of a digital signal processor and an associated dynamic random access memory. The digital signal processor provides significant data processing on the fly while the dynamic random access memory array provides additional buffering capability. Input and output FIFOs are connected to the data and address bussed of the digital signal processor. The control of the digital signal processor is via a host processor connected to the digital signal processor by a serial communication link.

REFERENCES:
patent: 4809161 (1989-02-01), Torii et al.
patent: 5412611 (1995-05-01), Hattori et al.
patent: 5438614 (1995-08-01), Rozman et al.

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