Variable redundancy cyclic code encoders

Details Variable redundancy cyclic code encoders Variable redundancy cyclic code encoders

2005-12-20

2005-12-20

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C708S492000, C714S785000

Reexamination Certificate

active

06978415

ABSTRACT:
A multiple-stage encoder encodes the data in accordance with one, two, . . . , or f factors of an associated cyclic code generator polynomial g(x)=g1(x)*g2(x)* . . . *gf(x) to produce data code words that include a selected number of ECC symbols. The encoder encodes the data d(x) in a first stage using a first factor gm(x) of a selected polynomial ps(x) to produce d(x)*xs=q1(x)g1(x)+r1(x), where q1(x) is a quotient and r1(x) is a remainder and g1(x) has degree s. In a next stage the encoder encodes q1(x) using a next factor gm(x) of the selected polynomial to produce qm(x)=q1(x)gm(x)+rm(x) and so forth, until the remainders associated with all of the factors of the selected generator polynomial have been produced. The system then manipulates the remainders to produce a remainder rs(x) that is associated with the selected polynomial ps(x), and uses a cyclically shifted version of the remainder rs(x) as the code word ECC symbols. The same circuitry is used to both produce and manipulate the remainders, and may also be used for decoding the code words in accordance with the selected polynomials.

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G. Fettweis, M. Hassner, “A Combined Reed-Solomon Encoder and Syndrome Generator with Small Hardware Complexity”, IBM Almaden Research Center, San Jose, CA, pp. 1871-1874.

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