Variable rate clock for timing recovery and method therefor

Details Variable rate clock for timing recovery and method therefor Variable rate clock for timing recovery and method therefor

1995-03-31

1999-02-23

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375376, H03D 324

Patent

active

058752188

ABSTRACT:
Apparatus and method are provided that can be advantageously included in a timing phase-locked loop for finally adjusting the period of a timing signal being controlled by that loop. The loop filter receives the timing signal and generates a loop error signal indicative of whether the period of the timing signal should be held the same, increased or decreased. A strobe signal is also generated each time that the timing signal is to be so corrected. The error signal and strobe signal are provided to a function generator such as a state machine. Each time that the function generator is strobed by the strobe signal, it produces a count signal whose value is representative of N, N+C or N-C, where N and C are integers and C represents a preset desired increment of change for the timing signal per strobe, i.e. the fineness of the adjustment of the timing signal. When not strobed by the strobe signal, the state machine produces a count signal of value N. When the state machine is strobed by the strobe signal and the error signal indicates that the timing signal should be held as is, the state machine remains in a first state such that the count signal has a value of N. If the state machine is strobed by the strobe signal and the error signal indicates that the period of the timing signal should be increased, then the state machine moves to a second state such that a digital count signal of N+C is generated once, after which the state machine returns to the first state. If the state machine is strobed by the strobe signal and the error signal indicates that the period of the timing signal should be decreased, then the state machine is moved to a third state such that a digital count signal of N-C is produced once, after which the state machine returns to the first state. The count signal is provided in parallel to a divide-by counter, which also receives a clock signal having a fixed frequency N times the frequency of the timing signal. The counter divides the clock signal by the value of the count signal to produce the timing signal. This timing signal is provided to the loop filter. The timing signal can also be used for example to clock in data.

REFERENCES:
patent: 4791488 (1988-12-01), Fukazawa et al.
patent: 4896337 (1990-01-01), Bushy, Jr.
patent: 5050195 (1991-09-01), Munter
patent: 5272730 (1993-12-01), Clark
patent: 5455847 (1995-10-01), Guilford et al.

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