Variable pulse width and pulse separation clock generator

Details Variable pulse width and pulse separation clock generator Variable pulse width and pulse separation clock generator

2005-05-10

2005-05-10

Wamsley, Patrick (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C327S263000, C327S291000

Reexamination Certificate

active

06891399

ABSTRACT:
A clock pulse generator for generating at least two clocked pulse signals from a global clock signal is provided. The clock pulse generator includes at least one input for receiving a clock signal having a rising and a falling edge and a mechanism for selectably delaying a rising edge of a pulse signal synchronized to the falling edge of the clock signal. The clock pulse generator further includes a first selectable duration pulse synchronized to the rising edge of the clock signal and a second selectable duration pulse synchronized to the selectably delayed rising edge. The clock pulse generator also includes a glitch avoidance circuit to remove glitches in the clock signal before it is used.

REFERENCES:
patent: 5008563 (1991-04-01), Kenney et al.
patent: 5221863 (1993-06-01), Motegi
patent: 5708381 (1998-01-01), Higashisaka
patent: 5712884 (1998-01-01), Jeong
patent: 5740410 (1998-04-01), McDermott
patent: 5805923 (1998-09-01), Shay
patent: 5861769 (1999-01-01), Black
patent: 5926053 (1999-07-01), McDermott et al.
patent: 5929682 (1999-07-01), Kazuya et al.
patent: 6067411 (2000-05-01), Poimboeuf et al.
patent: 6134182 (2000-10-01), Pilo et al.
patent: 6157226 (2000-12-01), Ishimi
patent: 6259283 (2001-07-01), Nguyen
patent: 6275446 (2001-08-01), Abedifard
patent: 6282210 (2001-08-01), Rapport et al.
patent: 6285226 (2001-09-01), Nguyen
patent: 6359481 (2002-03-01), Kim
patent: 6445644 (2002-09-01), Sher
patent: 6650145 (2003-11-01), Ngo et al.
patent: 6690204 (2004-02-01), Belluomini et al.
patent: 6798266 (2004-09-01), Vu et al.
Circuits and Systems for Limited Switch Dynamic Logic, having U.S. Appl. No. 10/116,612 and filed Apr. 4, 2002.
A Limited Switch Dynamic Logic Circuit, having U.S. Appl. No. 10/242,214 and filed Sep. 12, 2002.
Limited Switch Dynamic Selector Circuits, having U.S. Appl. No. 10/242,236 and filed Sep. 12, 2002.

Affiliated with

Also associated with

Rating

Variable pulse width and pulse separation clock generator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Variable pulse width and pulse separation clock generator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable pulse width and pulse separation clock generator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3412397