Variable pitch stagger die for optimal density

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond

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Details

257786, 438612, H01L 2348

Patent

active

058014500

ABSTRACT:
A bond pad layout for an integrated circuit die. The integrated circuit has four opposing sides that intersect at four corners of the die. The top surface of the integrated circuit has a plurality of bond pads that extend along each side of the die. The bond pads are typically coupled to corresponding bond fingers of an integrated circuit package by bond wires. The spacing pitch of the bond pads in the center portions of the die are smaller than the bond pad pitch at the corners of the die. The larger bond pad pitch at the corners of the die compensate for fanout of the bond wires. The smaller bond pad pitch in the center portions of the die optimizes the number of bond pads that can be formed on the integrated circuit. The bond pad layout thus optimizes the number of bond pads while compensating for the fanout of the bond wires.

REFERENCES:
patent: 4875138 (1989-10-01), Cusack

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