Variable memory refresh rate for DRAM

Details Variable memory refresh rate for DRAM Variable memory refresh rate for DRAM

2007-06-19

2007-06-19

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230030

Reexamination Certificate

active

10909705

ABSTRACT:
A method and apparatus for controlling a DRAM refresh rate. In one embodiment, a computer system includes a memory subsystem having a memory controller and one or more DRAM (dynamic random access memory) devices. The memory controller is configured to periodically initiate a refresh cycle to the one or more DRAM devices. The memory controller is also configured to monitor the temperature of the one or more DRAM devices. If the temperature exceeds a preset threshold, the memory controller is configured to increase the rate at which the periodic refresh cycle is performed.

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Sato, et al, “A 4-Mb Pseudo SRAM Operating a 2.6±1V with 3-μ A Data Retention Current”,IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991, pp. 1556-1562.

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