Variable mask field exposure

Details Variable mask field exposure Variable mask field exposure

2006-03-28

2006-03-28

Huff, Mark F. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Registration or layout process other than color proofing

C430S311000, C430S312000, C430S319000, C430S394000

Reexamination Certificate

active

07018753

ABSTRACT:
A method of fabricating integrated circuits according to a first design by imaging a first layer on a substrate using a first mask having a block of first patterns in common with a second design, but without any other patterns of the first or second designs and imaging a second layer on the substrate using a second mask having a block of second patterns unique to the first design and at least one third layer pattern. The block of first patterns is repeatedly exposed in a first grid and the block of second patterns is repeatedly exposed in a second grid, each without overlap in the corresponding layer. The grids are aligned such that the integrated circuits and test structures in scribe lines between the integrated circuits are properly formed on the substrate. The first patterns can be for large fields and the second patterns can be for small fields.

REFERENCES:
patent: 5175128 (1992-12-01), Ema et al.
patent: 5663017 (1997-09-01), Schinella et al.
patent: 5885749 (1999-03-01), Huggins et al.
patent: 6136517 (2000-10-01), Fletcher

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