Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2002-04-24
2004-04-20
Elms, Richard (Department: 2824)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S156000, C365S205000, C365S207000, C365S221000, C365S220000, C365S230060
Reexamination Certificate
active
06724647
ABSTRACT:
TECHNICAL FIELD
The present invention relates to techniques which can be effectively applied to design and manufacturing of a semiconductor integrated circuit or a logic integrated circuit, and more particularly, to a technique which can be effectively applied to a programmable logical LSI (large scaled integrated circuit) enabling configuration of any logic and a variable logical circuit suitable for formation of the LSI.
BACKGROUND ART
In design of a semiconductor integrated circuit such as design of a logic integrated circuit, in these years, its functional design is expressed in the form of hard description language (HDL) description at the initial stage of the product design. In accordance with such a design technique, simulation logic verification can be established in a short time, and a semiconductor integrated circuit (which will be referred to also as the logical LSI, hereinafter) can be developed to a gate level with use of a design support program called a logic synthesis tool provided from an engineering design automation (EDA) vendor. Further, since an automatic layout tool can convert data at the gate level to such layout data as to be able to form a circuit on a semiconductor chip, a developing period of time can be shortened to a large extent.
FIG. 14
shows a procedure of development of a logic integrated circuit utilizing the afore-mentioned HDL description, i.e., from its design to its trial manufacture. That is, in the development of the logic integrated circuit, the function design of the logic integrated circuit to be implemented is first conducted. Then designed functions are described in a language such as HDL. And design data (HDL-described statement) is previously stored in a storage device such as a hard disk as a data file. With respect to the HDL description, a support tool for automatically preparing an HDL-described statement based on a state transition diagram or a flowchart.
Next, a verifying program for generating a test pattern called a test vector from the design data described in HDL is used to verify whether or not its operation is proper. When a defect is found through the verification, the HDL-described statement is modified.
Thereafter, the HDL described design data is converted by a program called a logic synthesis tool to design data at logic gate level. Such a logic synthesis tool is also supplied from a plurality of EDA vendors. The generated design data at logic gate level is again verified based on the test vector. When a defect is found through the verification, the design data of logic gate level is modified.
On the basis of the design data of logic gate level, layout data at element level is generated by a program called an automatic layout tool. Such an automatic layout tool is also supplied from a plurality of EDA vendors. The generated layout data is simulated by the test vector in the form of actual load including wiring delay, improper portions are modified and optimized. Thereafter, on the basis of the generated layout data, mask pattern data is generated by an artwork, and on the basis of the generated data, a mask is prepared.
After that, a logic integrated circuit is formed on a semiconductor wafer in a previous step, and the wafer is cut into chips, each of which is sealed with sealing material such as resin and assembled into a package.
In such a design/manufacturing system as mentioned above, however, many design steps and many stages of design data generation are required until it is completed as a final logic integrated circuit device, thus involving increase in the amount of data. Further, in a system-on-chip wherein an entire system is configured on a single semiconductor chip, since many various functional circuit blocks are used and arranged, the number of steps of verifying and modifying the design data is increased, which becomes a big design problem.
In addition, in the prior art design technique, as an element is finer, the number of masks used to manufacture a single semiconductor integrated circuit is increased and more expensive manufacturing device is required for finer processing, thus resulting in increase of design and manufacturing costs and reduction of a yield.
In the prior art design technique, further, a mask is required to be manufactured separately for each product, with the result that a developing period of time for a new product is prolonged. Furthermore, products required by users in these years tend to be small in the quantity of product and many in the number of product types, thus imposing an increased design burden and therefore with an increased cost. In addition, in a fine processing of deep submicron (0.1 &mgr;m or less) which is expected to be realized in future, a synchrotron orbit radiation (SOR) device is indispensable. Thus, investment of semiconductor device manufacturers in miniaturization becomes difficult and the amount of investment in the miniaturization is approaching to its limit.
As a technique for coping with the limit of such a prior art LSI design technique as mentioned above, there is a logical LSI (U.S. Pat. No. 4,870,302) which is called a field programmable gate array (FPGA) or field programmable logic array (FPLA) and can be configured to an arbitrary logic by a user. Due to such a technique, since manufacturers can focus on development of base chips and take a mass production system, this technique is a promising technique in future.
However, in the case of a general FPGA, variable logical circuits and variable switch circuits are formed into separated cells respectively, and these cells are arranged on a semiconductor chip as filled with tiles all thereover, which results in a redundant circuit arrangement. In addition, the prior art FPGA has been arranged as a relatively large scale circuit such as, for example, a variable logical circuit made up of a plurality of memory cells and transmission gates. For this reason, the conventional FPGA has had a defect that a user logic mount efficiency is very low, that is, the scale of mountable user logic is smaller (about 30 -40%) than the percentage of the logic scale of the entire FPGA. Therefore, since the FPGA is larger in chip size than and smaller in yield than an application specific integrated circuit (ASIC) having the same logic scale, a device price becomes high and thus the application of the FPGA is limited.
It is an object of the present invention to provide a variable logical circuit which can be suitably used to configure a programmable semiconductor integrated circuit (FPLA) having a high user logic mount efficiency.
Another object of the present invention is to provide a variable logical circuit which can be suitably used to configure a semiconductor integrated circuit capable of being operated on a low voltage and of configuring an arbitrary logic.
Another object of the present invention is to provide a technique for designing a semiconductor integrated circuit or a method for manufacturing the circuit, which can remarkably reduce the number of design steps and a developing period of time.
A further object of the present invention is to provide a semiconductor integrated circuit, even when an element as a part of a manufactured product is defective, which can easily substitute the defect element by a normal one for its normal function with a high yield.
The above and other objects as well as novel features of the present invention will be apparent from the description of this specification and attached drawings.
DISCLOSURE OF INVENTION
In the present application, a summary of typical features of the present invention will be explained as follows.
A variable logical circuit in accordance with the present invention includes 2
n
(e.g., 4) memory cells which are alternatively selected according to a combination of ‘n’ pairs (e.g., two pairs) of positive and negative phase signals, and is arranged so as to output the positive and negative phase signals according to storage data in the selected memory cells.
Thus, a given number ‘n’ of input logic gates can be realized with the variable logical circuit
Saitoh Yoshikazu
Sato Masayuki
Shimizu Isao
Takahashi Hideaki
A. Marquez, Esq. Juan Carlos
Elms Richard
Fisher Esq. Stanley P.
Luu Pho M.
Reed Smith LLP
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