Variable load for margin mode

Details Variable load for margin mode Variable load for margin mode

1989-03-10

1992-08-25

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365201, 365104, 365185, 365210, 371 214, G11C 700, G11C 11413, G11C 2900

Patent

active

051424959

ABSTRACT:
An improvement in the margining circuit wherein a variable load is provided to a column of EPROM cells. A plurality of parallel transistors are coupled as the load and by controlling the number of transistors which are turned on, the voltage to the column can be adjusted, effectively adjusting the current to the cells.

REFERENCES:
patent: 4386419 (1983-05-01), Yamamoto
patent: 4612630 (1986-09-01), Rosier
patent: 4644196 (1987-02-01), Flannagan et al.
patent: 4760561 (1988-07-01), Yamamoto et al.
patent: 4780750 (1988-10-01), Nolan et al.
patent: 4809231 (1989-02-01), Shannon et al.
patent: 4841482 (1989-06-01), Kreifels et al.
patent: 4903265 (1990-02-01), Shannon et al.

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