Variable length delay circuit utilizing an integrated memory dev

Details Variable length delay circuit utilizing an integrated memory dev Variable length delay circuit utilizing an integrated memory dev

1994-02-08

1995-04-11

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Signals

365 78, 36518902, 36518912, 365240, G11C 700

Patent

active

054065186

ABSTRACT:
The present invention discloses an apparatus for receiving an ordered sequence of input data and for delaying the output of a delay output item by a variable-length delay-time. The apparatus includes an input port for receiving the ordered sequence of input data and the variable-length delay-time. The apparatus further includes an integrated data storage, a random access memory (RAM) for storing the ordered sequence of input data according to a storage-order corresponding to the ordered sequence of the input data. The apparatus further includes a delay output port for accessing and outputting the delay output item in the storage means according to the variable-length delay-time and the storage-order such that the delay output item is delayed by the variable-length delay-time.

REFERENCES:
patent: 4648077 (1987-03-01), Pinkham
patent: 4866675 (1989-09-01), Kawashima
patent: 4876670 (1989-10-01), Nakabayashi
patent: 4953128 (1990-08-01), Kawai

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