Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-10-05
2001-12-04
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S201000
Reexamination Certificate
active
06327217
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to memory devices and methods of operation thereof, and more particularly, to buffer circuits and methods of operation thereof.
Synchronous dynamic random access memory (SDRAM) devices typically output memory cell data in synchronization with a clock signal in response to an external command, e.g., a read command, that is received in synchronization with an external clock signal. The number of clock cycles occurring between the external command, which is synchronized with the external clock signal, and the output of data, which is synchronized with the clock signal, is often referred to as a latency number.
It may be desirable for an SDRAM device to operate over a range of clock frequencies. The maximum clock frequency of an SDRAM may be constrained by limits on minimum delay, jitter and skew of output data produced by the SDRAM. To increase the operating frequency of the SDRAM, latency in operation of output buffers may be introduced to allow sense amplifiers and other circuitry within the SDRAM to stabilize. However, when an SDRAM that operates with a latency designed for a relatively high clock frequency is operated at a relatively low clock frequency, the latency may introduce unnecessary delay in access time.
FIGS. 1 and 2
illustrates a part of a conventional SDRAM
1
and exemplary operations thereof. Memory cell data is transmitted through an internal circuit
2
to a data line DIO, and on to an output pad DQ via a latch circuit LAT
1
and an output buffer
3
. The signal applied to the output buffer is delayed by a time Del
1
, which is predominantly introduced by the internal circuit
2
. A data hold signal hold is asserted to a logic high level, so that the memory cell data on the data line DIO is transmitted to the output buffer
3
.
Referring to
FIG. 2
, first, second and third time intervals are defined, each corresponding to approximately a half the clock cycle of a clock signal (CLK). The first, second and third intervals denote latency intervals, i.e., latency may be determined according to which among the first, second and third intervals the delay time Del
1
of
FIG. 1
falls, with the first interval representing a latency of 1, the second interval representing a latency of 1.5, and the third interval representing a latency of 2. For example, as shown in
FIG. 2
, memory cell data having a delay time Del
1
falling within the third interval following the rising edge of the clock signal CLK that coincides with a data read command READ is transmitted to the data line DIO with a latency of 2. Accordingly, valid data of the memory cell data is output to the output pad DQ two clock cycles after the rising edge of the clock signal CLK that coincides with the data read command READ.
Still referring to
FIG. 2
, if the SDRAM
1
that operates with a latency of 2 for a relatively high frequency clock CLK as described above is used with a lower clock frequency CLK_
1
, however, memory cell data which has passed through the internal circuit block
2
arrives at the data line DIO delayed by the delay time Del
1
after the rising edge of a clock signal CLK_
1
that coincides with the data read command READ. Under these conditions, a time loss T
LOSS
with respect to the operation with the higher frequency clock signal CLK may be incurred. This may degrade operating performance.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, a latency determination circuit includes a latency interval definition circuit that receives a clock signal and that generates at least one latency interval defining signal that defines at least one latency interval. A latency indication circuit receives the at least one latency interval defining signal and a test signal that is delayed a predetermined delay with respect to the clock signal and generates a latency indicating signal therefrom. The latency determination circuit may further include a test signal generation circuit configured to receive the clock signal and operative to produce the test signal therefrom.
In some embodiments of the present invention, the test signal generation circuit is configured to receive a control signal and to generate the test signal therefrom such that the test signal is delayed the predetermined delay with respect to a next occurring feature, e.g., edge, of the clock signal following assertion of the control signal. The test signal generation circuit may include a synchronization circuit that receives the control signal and the clock signal and that generates a synchronized control signal from the control signal, and a delay circuit that produces the test signal from the synchronized control signal.
In other embodiments of the present invention, the latency interval definition circuit is operative to successively generate respective edges in respective ones of a plurality of latency interval defining signals responsive to successive edges of the clock signal. The latency interval definition circuit may be responsive to a control signal and operative to successively generate the respective edges in the respective ones of the plurality of latency interval defining signals following transition of a control signal to a predetermined logic level. In other embodiments of the present invention, the latency indication circuit is operative to assert a first latency indicating signal responsive to the test signal transitioning to a predetermined logic state before a first edge of the successively generated edges and to assert a second latency indicating signal responsive to the test signal transitioning to the predetermined logic state between the first edge and an immediately succeeding second edge of the successively generated edges.
According to still other embodiments of the present invention, a variable delay buffer circuit, as might be used in a synchronous DRAM, includes a buffer circuit that receives an input signal and generates an output signal therefrom responsive to an output enable signal. An output enable signal generation circuit receives a latency indicating signal and generates the output enable signal responsive to the command signal with a delay that is based on the latency indicating signal. A latency interval definition circuit receives a clock signal and generates at least one latency interval defining signal that defines at least one latency interval. A latency indication circuit receives the at least one latency interval defining signal and a test signal that is delayed a predetermined delay with respect to the clock signal and generates the latency indicating signal therefrom. The predetermined delay may approximate, for example, a sum of a delay associated with the buffer circuit and a delay associated with a circuit that provides the input signal to the buffer circuit.
Related methods are also discussed.
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patent: 5384750 (1995-01-01), Lee
patent: 5424983 (1995-06-01), Wojcicki et al.
patent: 5568445 (1996-10-01), Park et al.
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patent: 5835444 (1998-11-01), Kim et al.
patent: 5933379 (1999-08-01), Park et al.
patent: 6023177 (2000-02-01), Kim et al.
patent: 6157992 (2000-12-01), Sawada et al.
patent: 6192429 (2001-02-01), Jeong et al.
Myers Bigel & Sibley & Sajovec
Phan Trong
Samsung Electronics Co,. Ltd.
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