Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Patent
1997-11-14
1999-08-10
Sheikh, Ayaz R.
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
710127, G06F 1300
Patent
active
059352329
ABSTRACT:
A system and method for choosing communication pathways for data transfers on a computer chip based on desired latency and bandwidth characteristics. On a computer chip including a network of resources, those resources are allocated based upon the needs of the various components of the computer chip. Typical resources on the computer chip include a first bus with a plurality of data lines and control lines and having first bandwidth and latency characteristics, a second bus with a plurality of data lines and control lines having second bandwidth and latency characteristics, and a plurality of devices coupled to the first bus and second bus. Each device includes interface logic for accessing and performing transfers on the first and second buses. Each device is operable to select either the first or second bus depending on desired bandwidth and latency characteristics. Normally the first bandwidth is greater than the second bandwidth. Each device selects the first bus for higher speed transfers or the second bus for lower speed transfers. When the first latency is shorter than the second latency, each of the devices select the first bus for lower latency transfers and the second bus for higher latency transfers. Other characteristics which may be varies by each device according to the transmission needs of the particular device include clock rate, block size, and bus protocol depending upon desired bandwidth and latency characteristics. For highest possible bandwidth transfers, a multiple bus transfer may be requested by any device.
REFERENCES:
patent: 4096571 (1978-06-01), Vander Mey
patent: 4339808 (1982-07-01), North
patent: 4682282 (1987-07-01), Beasley
patent: 4953081 (1990-08-01), Feal et al.
patent: 4972313 (1990-11-01), Getson, Jr. et al.
patent: 4974148 (1990-11-01), Matteson
patent: 5146596 (1992-09-01), Whittaker et al.
patent: 5245322 (1993-09-01), Dinwiddie, Jr. et al.
patent: 5265223 (1993-11-01), Brockmann et al.
patent: 5274763 (1993-12-01), Banks
patent: 5274784 (1993-12-01), Arimilli et al.
patent: 5278974 (1994-01-01), Lemmon et al.
patent: 5345566 (1994-09-01), Tanji et al.
patent: 5392033 (1995-02-01), Oman et al.
patent: 5396602 (1995-03-01), Amini et al.
patent: 5404463 (1995-04-01), McGarvey
patent: 5463624 (1995-10-01), Hogg et al.
patent: 5467454 (1995-11-01), Sato
patent: 5471590 (1995-11-01), Melo et al.
patent: 5524235 (1996-06-01), Larson et al.
patent: 5526017 (1996-06-01), Wilkie
patent: 5533205 (1996-07-01), Blackledge, Jr. et al.
patent: 5535341 (1996-07-01), Shah et al.
patent: 5546546 (1996-08-01), Bell et al.
patent: 5572686 (1996-11-01), Nunziata et al.
patent: 5574867 (1996-11-01), Khaira
patent: 5583999 (1996-12-01), Sato et al.
patent: 5606557 (1997-02-01), Kuroshita et al.
patent: 5627975 (1997-05-01), Bryant et al.
patent: 5627976 (1997-05-01), McFarland et al.
patent: 5682484 (1997-10-01), Lambrecht
patent: 5710892 (1998-01-01), Goodnow et al.
patent: 5748806 (1998-05-01), Gates
patent: 5754548 (1998-05-01), Hoekstra et al.
patent: 5754807 (1998-05-01), Lambrecht et al.
Itano, et al "HIRB: A Hierarchical Ring Bus" University of Tsukuba, Japan, Proceedings of the Nineteenth Annual Hawaii International Conference on System Sciences, 1986, pp. 206-213.
Kim, et al, "A Relational Dataflow Database Machine Based on Heirarchical Ring Network," Korea Advanced Institute of Technology, Proceedings of the International Conference on Fifth Generation Computer Systems, 2984, pp. 489-496.
Su, et al, "Adaptive Fault-Tolerant Deadlock-Free Routing of the Slotted Ring Multiprocessor," IEEE Transactions on Computers, vol. 45, No. 6, Jun. 1996, pp. 666-683.
Gustavson, D.B., "Scalable Coherent Interface and Related Standards Projects," IEEE vol. 12, No. 1, pp. 10-22, Feb. 1992.
Cha, et al, "Simulated Behaviour of Large Scale SCI Rings and Tori," Depts. of Engineering and Computer Science, University of Cambridge, United Kingdom, pp. 1-21, Proceedings of 5th IEEE Symposium on Parallel and Distributed Processing, Dallas, Texas, Dec. 1993.
Franklin, et al, "ARB: A Hardware Mechnism for Dynamic Reordering of Memory References," IEEE Transactions on Computers, vol. 45, No. 5, May 1996, pp. 552-571.
Barroso, et al, "Performance Evaluation of the Slotted Ring Multiprocessor," IEEE Transactions on Computers, vol. 44, No. 7, Jul. 1995, pp. 878-890.
Bhuyan, et al, "Approximate Analysis of Single and Multiple Ring Networks," IEEE Transactions on Computers, vol. 38, No. 7, Jul. 1989, pp. 1027-1040.
Arden, et al, "Analysis of Chordal Ring Network," IEEE Transactions on Computers, Vo. C-30, No. 4, Apr. 1981, pp. 291-301.
Kubiatowicz et al, "The Alweife CMMU: Addressing the Multiprocessor Communications Gap," Extended Abstract for Hot Chips '94, 1994, pp. 1-3.
Kubiatowicz et al, "The Anatomy of a Message in the Alewife Multiprocessor," Proceedings of the International Conference on Supercomputing (ICS) 1993, pp. 195-206, Jul. 1993.
PCI Local Bus-PCI Multimedia Design Guide-Revision 1.0-Mar. 29, 1994.
IBM Technical Disclosure Bulletin, Apr. 1995, vol. 38, "Micro Channel Architecture for Real Time Multimedia," pp. 535-538.
IBM Technical Disclosure Bulletin, Oct. 1992, vol. 35, "Extended Micro Channel for Realtime Multimedia Applications," pp. 8-10.
IBM Technical Disclosure Bulletin, May 1989, vol. 31, "Priority Scheduling Algorithm," pp. 271-272.
Patent Abstracts of Japan, JP2048765, Feb. 19, 1990.
Peripheral Component Interconnect (PCI) Revision 1.0 Specification, Jun. 22, 1992, cover page and pp. 26-33.
Hartmann Alfred C.
Lambrecht J. Andrew
Advanced Micro Devices , Inc.
Hood Jeffrey C.
Iselin Louis H.
Pancholi Jigar
Sheikh Ayaz R.
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