Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-12-31
2004-03-16
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S104000, C712S207000, C365S230030
Reexamination Certificate
active
06708255
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a variable input/output control device.
DESCRIPTION OF THE PRIOR ART
Generally, a memory has a fixed prefetch way, which is an input/output way so that an SDRAM fabricated with a 1-bit prefetch way cannot be used as a DDR SDRAM using a 2-bit prefetch way. Also, the DDR SDRM fabricated with a 2-bit prefetch way cannot be used as a SDRAM using a 1-bit prefetch way. Accordingly, utility of the memory is low.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor memory device having a variable input/output control device.
In accordance with an aspect of the present invention, there is provided a variable input/output control device in a synchronous semiconductor memory device, comprising a plurality of first prefetch units to prefetch data from an input buffer; a plurality of second prefetch units to prefetch data from a memory core; and a control signal generating means for generating a control signal in response to command signals to select one of the plurality of first prefetch units and one of the plurality of second prefetch units.
In accordance with another aspect of the present invention, there is provided a variable input/output control device in a synchronous semiconductor memory device, comprising a first N-bit prefetch unit to prefetch data from an input buffer; a second N-bit prefetch unit to prefetch data from a memory core; and a means for determining the number of prefetch bits in the first and second N-bit prefetch units in response to a command signal.
REFERENCES:
patent: 5822577 (1998-10-01), Ekanadham et al.
patent: 6351427 (2002-02-01), Brown
patent: 6430092 (2002-08-01), Nanba
patent: 2002/0024882 (2002-02-01), Ikeda
patent: 2002/0071316 (2002-06-01), Manning
patent: 2002/0105836 (2002-08-01), Benedix
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Moazzami Nasser
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