Variable impedance output buffer

Details Variable impedance output buffer Variable impedance output buffer

2006-08-22

2006-08-22

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S031000, C326S032000, C326S033000, C326S034000, C326S082000, C326S083000, C326S085000, C326S086000, C326S087000

Reexamination Certificate

active

07095246

ABSTRACT:
An output buffer circuit (10, 40, 50) includes an output driver transistor (12), a predriver circuit (14, 54), and a bias generator (16, 54). The predriver circuit (14, 54) has an input terminal for receiving an input signal (IN), a first terminal coupled to a power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the transistor (12). The bias generator (16, 54) is coupled to the second terminal of the predriver circuit (14, 54), and provides a bias voltage (VG) to the second terminal of the predriver circuit (14, 54) for controlling the gate voltage of the output driver transistor (12).

REFERENCES:
patent: 4918336 (1990-04-01), Graham et al.
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patent: 6362655 (2002-03-01), Abraham
patent: 6560290 (2003-05-01), Ahn
patent: 6664821 (2003-12-01), De Haas
patent: 6737886 (2004-05-01), Curatolo
patent: 6753738 (2004-06-01), Baird
patent: 6836173 (2004-12-01), Yang
patent: 6903588 (2005-06-01), Vorenkamp

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