Variable fixed multipliers using memory blocks

Details Variable fixed multipliers using memory blocks Variable fixed multipliers using memory blocks

2005-09-13

2005-09-13

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S040000, C708S505000, C708S670000, C708S625000

Reexamination Certificate

active

06943579

ABSTRACT:
A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the second multi-bit calculation result by at least one bit to generate a shifted second multi-bit calculation result. A multi-bit adder coupled to the at least one RAM block adds the shifted second multi-bit calculation result to the first multi-bit calculation result.

REFERENCES:
patent: 5550782 (1996-08-01), Cliff et al.
patent: 6118720 (2000-09-01), Heile
patent: 6249143 (2001-06-01), Zaveri et al.
patent: 6255849 (2001-07-01), Mohan
patent: 6438570 (2002-08-01), Miller
patent: 6584481 (2003-06-01), Miller
Altera Technical Brief 5, (Mar. 1996). “Implementing Multipliers in FLEX 10K EABs,” 2 pages.
Altera, (Feb. 1998). “Implementing FIR Filters in FLEX Devices,” 1.01, pp 1-24.
Altera, (May 2001). “Implementing Logic with the Embedded Array in FLEX 10K Devices” ver. 2.1, pp 1-20.
U.S. Appl. No. 10/140,311, filed May 6, 2002, Hanzanchuk.

Affiliated with

Also associated with

Rating

Variable fixed multipliers using memory blocks does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Variable fixed multipliers using memory blocks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable fixed multipliers using memory blocks will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3372934