Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With bumps on ends of lead fingers to connect to semiconductor
Reexamination Certificate
2009-08-13
2011-12-13
Pert, Evan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With bumps on ends of lead fingers to connect to semiconductor
C257S780000, C257S782000, C257SE21511, C438S612000, C438S613000
Reexamination Certificate
active
08076762
ABSTRACT:
A packaged semiconductor product includes a packaging substrate coupled to a semiconductor die through an interconnect structure with elements of variable features. The interconnect structure may be bumps or pillars. The variable features of the interconnect structure induce a reverse bend on the semiconductor die that mitigates warpage of the semiconductor die during semiconductor assembly by balancing bending of the packaging substrate during reflow. The variable features can be variable height and/or variable composition.
REFERENCES:
patent: 5435482 (1995-07-01), Variot et al.
patent: 6109507 (2000-08-01), Yagi et al.
patent: 6396159 (2002-05-01), Shoji
patent: 6527159 (2003-03-01), Matthies et al.
patent: 2003/0010807 (2003-01-01), Matthies et al.
patent: 9246324 (1997-09-01), None
patent: 9840912 (1998-09-01), None
International Search Report and Written Opinion—PCT/US2010/045499, International Search Authority— European Patent Office—Feb. 24, 2011.
Partial International Search Report—PCT/US2010/045499—International Search Authority, European Patent Office, Dec. 8, 2010.
Scheifers S M et al: “A Novel Method of Minimizing Printed Wire Board Warpage”, Motorola Technical Developments, Motorola Inc., Schaumburg, Illinois, US, vol. 28, Aug. 1, 1996, pp. 50-55, XP000638420, ISSN: 0887-5286.
Tu K N. et al: “Physics and materials challenges for lead-free solders”, Journal of Applied Physics, American Institute of Physics. New York, US, vol. 93, No. 3, Feb. 1, 2003, pp. 1335-1353, XP012058916, ISSN: 0021-8979, DOI: 10.1063/1.1517165 pp. 1349-1350, section “Thermal stress”.
3, Feb. 1, 2003, pp. 1335-1353, XP012058916, ISSN: 0021-8979, DOI: 10.1063/1.1517165 pp. 1349-1350, section “Thermal stress”.
Chandrasekaran Arvind
Radojcic Ratibor
Gallardo Michelle
Pauley Nicholas J.
Pert Evan
QUALCOMM Incorporated
Velasco Jonathan T.
LandOfFree
Variable feature interface that induces a balanced stress to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Variable feature interface that induces a balanced stress to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable feature interface that induces a balanced stress to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4261119