Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-02-23
2001-07-31
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S202000, C365S203000
Reexamination Certificate
active
06269037
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to testing of semiconductor memory devices, such as dynamic random access memory devices, and in particular, the invention relates to a method and circuit for adjusting an equilibrate voltage of paired digit lines of a memory device.
BACKGROUND OF THE INVENTION
Semiconductor memory devices, such as dynamic random access memory (DRAM) devices typically store data as a logic one or zero. The data is represented as a charge stored on a capacitor. The charge is shared with a second capacitor, such as a digit line, to produce a resultant voltage. The voltage is then compared to a reference voltage to determine the correct data state. That is, a resultant voltage greater than the reference voltage is a one, and a resultant voltage less than the reference voltage is a zero.
Prior to any memory access cycle, for normal operation of the memory and during of the memory, paired digit lines are equilibrated to common potential, typically one-half the supply voltage Vcc. Memory devices include equilibration circuits for this purpose. The equilibration circuit typically comprises one or more transistors that are connected between the digit lines that form a pair of paired digit fines. These transistors are enabled by an equilibrate enable signal that is provided prior to the start of a memory access cycle. When enabled, the transistors short the paired digit lines together. In a differential sensing scheme, the digit lines are charged to opposite supply voltage potentials. Thus, the resultant equilibrate voltage is ½ Vcc.
When testing an integrated circuit memory device it is useful to test memory cell margins, or the amount of voltage a memory cell can move a digit line above an equilibrate voltage. As such, a memory cell with a small margin may result in erroneous data storage. This is particularly true if the memory cell is partially discharged prior to a data read operation. A separate bias voltage can be coupled to a digit line prior to reading data stored in the memory to stress cell margins. This technique is unattractive because of the relative slowness of changing the equilibrate voltage after the standard equilibrate operation is completed.
For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method and circuit for rapidly equilibrating paired digit lines of a semiconductor memory to a variable voltage, such as during testing.
SUMMARY OF THE INVENTION
The present invention provides a circuit fabricated in an integrated circuit memory device for equilibrating paired digit lines of a memory. The circuit allows the digit lines to be quickly equilibrated to an equilibrate voltage which is different than an equilibrate voltage used during normal memory operations.
In accordance with one embodiment of the invention, there is provided a memory device comprising an array of memory cells arranged in rows and columns, a digit line pair located in the array, and a sense amplifier circuit coupled to the digit line pair for sensing and amplifying a differential voltage between the digit line pair. The memory device also comprises a bias circuit coupled to the sense amplifier circuit for providing a bias voltage to one digit line of the digit line pair during a test operation, and an equilibrate circuit coupled to the digit line pair for equilibrating the digit line pair to a common voltage.
In another embodiment, a Dynamic Random Access Memory comprises an array of memory cells arranged in rows and columns, first and second digit lines arranged as a digit line pair and located in the array, and a sense amplifier circuit coupled to the first and second digit lines for sensing and amplifying a differential voltage between the first and second digit lines. The sense amplifier comprises first and second cross coupled transistors. The first transistor having a drain coupled to the first digit line, a gate coupled to the second digit line, and a source coupled to a source of the second transistor. The second transistor having a drain coupled to the second digit line, and a gate coupled to the first digit line. A pull-up transistor is coupled between the source of the second transistor and a bias voltage, the pull-up transistor controlled by an activate signal coupled to its gate. An equilibrate circuit is coupled to the digit line pair for equilibrating the first and second digit lines to a common equilibrate voltage.
In yet another embodiment, a method of equilibrating a memory device during a test mode is described. The method comprises the steps of initiating a test mode, accessing a memory cell for either reading from or writing data to the memory cell, and activating sense amplifier circuitry. The sense amplifier detects a differential voltage between complementary digit lines, and drives a first digit line to a high voltage and a second digit line to a low voltage. The method further comprises isolating the memory cell, activating a bias circuit to raise the second digit line voltage, and coupling the complementary digit lines together to equilibrate the first and second digit lines to a common test equilibrate voltage A method of testing memory cell margin in a memory device is also described. The method comprises the steps of equilibrating first and second digit lines to a first level, reading data stored in a memory cell, and restoring the data to a memory cell. The first and second digit lines ire equilibrated to a second level which is greater than the first level via a bias circuit and sense amplifier. The steps of re-reading the data stored in the memory cell, and equilibrating the first and second digit lines to successively higher equilibrate voltages until a data read error is detected are also included in the method.
REFERENCES:
patent: 4916668 (1990-04-01), Matsui
patent: 4967395 (1990-10-01), Watanabe et al.
patent: 5132575 (1992-07-01), Chern
patent: 5245578 (1993-09-01), McLaury
patent: 5302870 (1994-04-01), Chern
patent: 5369317 (1994-11-01), Casper et al.
patent: 5555523 (1996-09-01), Haga et al.
patent: 5677886 (1997-10-01), Seo et al.
patent: 5680344 (1997-10-01), Seyyedy
patent: 5701268 (1997-12-01), Lee et al.
patent: 5732033 (1998-03-01), Mullarkey et al.
patent: 5862089 (1999-01-01), Raad et al.
patent: 5877993 (1999-03-01), Biegel et al.
patent: 5912853 (1999-06-01), Rao
patent: 6052322 (2000-04-01), Beigel et al.
Hoang Huan
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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