Variable equilibrate voltage circuit for paired digit lines

Details Variable equilibrate voltage circuit for paired digit lines Variable equilibrate voltage circuit for paired digit lines

1997-11-25

1999-05-11

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Testing

365203, 365205, 365207, 365202, G11C7/00

Patent

active

059035021

ABSTRACT:
A method and circuit for rapidly equilibrating paired digit lines of a memory array of a dynamic random access memory device is described. The equilibrate circuit includes a bias-circuit coupled to sense amplifier circuitry for adjusting the equilibrate voltage during testing. A method is described for testing memory cell margin by adjusting the equilibrate voltage until an error is detected. The bias circuit is described as a pull-up transistor coupled to a common mode of a cross-coupled n-sense amplifier.

REFERENCES:
patent: 4967395 (1990-10-01), Watanabe et al.
patent: 5132575 (1992-07-01), Chern
patent: 5245578 (1993-09-01), McLaury
patent: 5302870 (1994-04-01), Chern
patent: 5369317 (1994-11-01), Casper et al.
patent: 5680344 (1997-10-01), Seyyedy

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