Variable digital delay circuit

Details Variable digital delay circuit Variable digital delay circuit

1982-06-14

1985-03-19

Popek, Joseph A.

Static information storage and retrieval

Recirculation stores

365189, 365230, G11C 700

Patent

active

045063486

ABSTRACT:
A variable digital delay circuit is disclosed which utilizes a shift register to periodically sample a signal to be delayed and after a predetermined number of samples are collected as a group of zeros and ones making up a binary word the word is stored in parallel in a memory. After each binary word is stored in a memory a binary word previously stored in the memory is read out into a buffer store from which each individual bit is sequentially read out using a multiplexer at the same rate that the bits were originally taken to thereby recreate the original signal samples. The time delay is determined by how long the previously stored binary word being read out has been stored in the memory.

REFERENCES:
patent: 3596259 (1971-07-01), Teramura et al.
patent: 4156286 (1979-05-01), Connors et al.
patent: 4400801 (1983-08-01), Kible

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