Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1998-02-13
2000-06-06
Tokar, Michael
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 41, H03K 19177
Patent
active
060723327
ABSTRACT:
A programmable logic device, which includes a plurality of regions of memory usable by a user of the device, has circuitry for facilitating stringing or chaining together multiple memory regions to produce memory that is deeper than one region.
REFERENCES:
patent: 4642487 (1987-02-01), Carter
patent: 4670749 (1987-06-01), Freeman
patent: 4706216 (1987-11-01), Carter
patent: 4758985 (1988-07-01), Carter
patent: 4870302 (1989-09-01), Freeman
patent: 5089993 (1992-02-01), Neal et al.
patent: 5128559 (1992-07-01), Steele
patent: 5237219 (1993-08-01), Cliff
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5469400 (1995-11-01), Yamano
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5689195 (1997-11-01), Cliff et al.
John L. Nichols, "A Logical Next Step for Read-Only Memories", Electronics, Jun. 12, 1967, pp. 111-113.
Floyd Kvamme, "Standard Read-Only Memories Simplfy Complex Logic Design", Electronics, Jan. 5, 1970, pp. 88-95.
Albert Hemel, "Making Small ROM's [sic] Do Math Quickly, Cheaply and Easily", Electronics, May 11, 1970, pp. 104-111.
William I. Fletcher et al., "Simplify Sequential Circuit Designs", Electronic Design, Jul. 8, 1971, pp. 70-72.
S.C. Hu, "Cellular Synthesis of Synchronous Sequential Machines", IEEE Transactions on Computers, Dec. 1972, pp. 1399-1405.
E.W. Page, "Programmable Array Realizations of Sequential Machines, "Department of Electrical Engineering, Duke University, Doctoral Dissertation, 1973.
Howard A. Sholl et al., "Design of Asynchronous Sequential Networks Using Read-Only Memories", IEEE Transactions on Computers, vol. C-24, No. 2, Feb. 1975, pp. 195-206.
Arnold Weinberger, "High-Speed Programmable Logic Array Adders", IBM J. Res. Develop., vol. 23, No. 2, Mar. 1979, pp. 163-178.
Yahiko Kambayashi, "Logic Design of Programmable Logic Arrays", IEEE Transactions on Computers, vol. C-28, No. 9, Sep. 1979, pp. 609-617.
"Optimized Reconfigurable Cell Array (ORCA) Series Field-Programmable Gate Arrays," Advanced Data Sheet, Feb. 1993, AT&T Microelectronics, pp. 1-87.
The Programmable Logic Data Book, Xilinx, Inc., 1994, pp. 2-5 through 2-102 .
Altera Corporation
Jackson Robert R.
Le Don Phu
Sharifi Pejman
Tokar Michael
LandOfFree
Variable depth memories for programmable logic devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Variable depth memories for programmable logic devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable depth memories for programmable logic devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2216452