Variable delay oscillator buffer

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Reexamination Certificate

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07983375

ABSTRACT:
A novel and useful variable delay digitally controlled crystal oscillator (DCXO) buffer (i.e. slicer). A conventional slicer following the DCXO is modified to introduce a controlled random variable delay into the buffered DCXO clock. The resultant output clock signal is then used as input to the TDC of an ADPLL circuit to alleviate the subharmonic mixing based deterioration caused by LO/TX coupling through the crystal pins, and to alleviate the dead-beat effects caused by the finite resolution of the TDC. Two mechanisms for introducing variable delay into the buffered DCXO output clock signal are presented: a first mechanism that creates variable delay in fine steps and a second mechanism that creates variable delay in coarse steps. In both mechanisms, switches are incorporated into the slicer circuitry and controlled using digital bit sequences which may comprise dithering signals. The switches are turned on and off via the digital bit sequences which varies the delay of the slicer clock output which serves to shift the rising and falling transition points of the resultant output clock signal. The jitter is shifted to higher frequencies where it is filtered out by the PLL loop filter.

REFERENCES:
patent: 6809598 (2004-10-01), Staszewski et al.
patent: 2006/0033582 (2006-02-01), Staszewski et al.
patent: 2006/0038710 (2006-02-01), Staszewski et al.
patent: 2006/0208779 (2006-09-01), Lin et al.
patent: 2006/0226881 (2006-10-01), Jaussi et al.
U.S. Appl. No. 11/853,182, filed Sep. 2007, Sheba et al.
U.S. Appl. No. 11/832,292, filed Aug. 2007, Entezari et al.

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