Measuring and testing – Instrument proving or calibrating – Timing apparatus
Reexamination Certificate
2000-09-21
2002-12-31
Raevis, Robert (Department: 2856)
Measuring and testing
Instrument proving or calibrating
Timing apparatus
Reexamination Certificate
active
06499334
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-268352, filed Sep. 22, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a variable delay element test circuit. Further, the present invention relates to a test circuit used for measuring variable delay element delay characteristics, during the success or failure decision made after product shipping inspection, reception inspection or system integration of variable delay elements.
Now, the prior art for measuring delay characteristics of variable delay elements used for various measuring instruments such as pulse generator and LSI tester timing generation section, or timing adjustment circuit in an LSI shall be described typically below.
A first prior art is a method for searching for variation points of “H” edge or “L” edge of a signal delayed by a delay time corresponding to a control signal by a variable delay element to be measured, using a reference signal at the side of measuring instrument, for instance, LSI tester or individual measuring instrument, and finding edge boundaries.
A second prior art is a technique used generally for evaluating AC characteristics of an LSI and is a method for constituting a ring oscillator in a way to contain a variable delay element to be measured, measuring by frequency measuring instrument the ring oscillator oscillation frequency before and after the variation of delay amount of the variable delay element, and determining the delay amount from the variation of oscillation frequency.
A third prior art is a technique using phase difference/voltage conversion and is a method for integrating a pulse signal corresponding to the phase difference between a signal to be measured that has passed through the variable delay element and the reference signal, converting into voltage and A/D converting this voltage value to determine the delay amount.
Now, inconveniences of these prior arts will be described below.
The first prior art requires an LSI tester having high performance or individual measuring instrument, and the running cost of measuring environment becomes expensive, because, if there is a plurality of variable delay elements, it is necessary to test each delay element one by one. Moreover, it is necessary to exchange data between the measurement system and the control system, because it is necessary to control the timing of reference signal used for search by a control system using a CPU or the like, when edge boundary is to be detected during the search of signal “H” edge, “L”, edge variation points, thus requiring a considerable processing time.
In the second prior art, given the circuit restriction of the ring oscillator, it is necessary to measure the duty ratio, when a test is to be performed with respect to either one of rising or dropping of a signal output from the ring oscillator, thus requiring special circuits or measuring instruments. In addition, as in the aforementioned first prior art, it is necessary to exchange data between the measurement system and the control system, thus requiring a considerable processing time.
In the third prior art, settling time is necessary for the A/D conversion of integrated voltage value, thus requiring a considerable processing time as in previous two examples. Moreover, it is necessary to adapt the aforementioned integrated voltage value to the voltage range of the A/D converter.
This third prior art is certainly more effective than the aforementioned two examples; however, error will occur due to jitter generated in the signal transmission system or A/D converter or to the measurement system characteristics, when the delay variation amount of the variable delay element is minute. Besides, the reproducibility of measurement data can not be assured.
As described above, the conventional variable delay element test circuit of the method constituting ring oscillator including the variable delay element to be measured requires special circuits or measuring instruments when a test is to be performed with respect to either one of rising or dropping of ring oscillator signal, and it is necessary to exchange data between the measurement system and the control system, thus requiring a considerable processing time.
BRIEF SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a variable delay element test circuit for measuring with high accuracy a fine delay time variation amount, event when the delay time variation amount of the variable delay element is extremely small and, allowing to decide success or failure of variable delay element rapidly with a high precision.
According to a first aspect of the present invention, there is provided a variable delay element test circuit comprising a variable delay element having an input node and an output node, a delay time amount to output by delaying an input pulse signal input to the input node being set arbitrarily; a loop control circuit having a loop circuit, the variable delay element being included in this loop circuit, for controlling so that the positive
egative logic of the input pulse signal input to the input node of the variable delay element is always constant; a count control circuit for receiving an output pulse signal output from the output node of the variable delay element, counting the number of receptions of this output pulse signal, detecting agreement of that count value and a predetermined set value, and for generating an agreement detection signal when the agreement is detected; and an output control circuit connected to the count control circuit, for controlling the transmission of the output pulse signal output from the variable delay element to following circuits of the variable delay element, based on the agreement detection signal-generated by the count control circuit.
According to a second aspect of the present invention, there is provided a variable delay element test circuit comprising a first variable delay element having an input node and an output node, a delay time amount to output by delaying a first input pulse signal input to the input node being set arbitrarily; a loop, control circuit having a loop circuit, the first variable delay element being included in this loop circuit, for controlling so that the positive
egative logic of the first input pulse signal input to the input node of the first variable delay element is always constant; a count control circuit for receiving an output pulse signal output from the output node of the first variable delay element, counting the number of receptions of this output pulse signal, detecting agreement of that count value and a predetermined set value, and for generating an agreement detection signal when the agreement is detected; and an output control circuit connected to the count control circuit, for controlling the transmission of the output pulse signal output from the variable delay element to following circuits of the variable delay element, based on the agreement detection signal generated by the count control circuit; wherein the loop control circuits comprises a second variable delay element having an input node and an output node, a second input pulse signal having a logic opposite to the logic of the first input pulse signal input into the input node of the first variable delay element being supplied to the input node of the second variable delay element; a flip-flop circuit having a set signal input node, a reset signal input node and an output node, the set signal input node of the flip-flop circuit being connected to the output node of the first variable delay element, and the reset signal input node of the flip-flop circuit being connected to the output node of the second variable delay element; and a feedback circuit for feeding back signal output from the output node of the flip-flop circuit to the input node of the first variable delay element; and wherein the first variable delay element,
Foley & Lardner
Kabushiki Kaisha Toshiba
Raevis Robert
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