Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2011-06-07
2011-06-07
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Read/write circuit
Signals
C365S076000, C365S093000
Reexamination Certificate
active
07957210
ABSTRACT:
A variable delay circuit being able to change a delay amount from when a signal is inputted to when the signal is outputted has a first delay section delaying the signal by a first delay amount, a second delay section delaying the signal by a second delay amount greater than the first delay amount, and a delay amount selector selecting a signal route where the delay amount is a sum of the first delay amount and the second delay amount when the delay amount exceeds a maximum delay amount delayable by the first delay amount section. The delay amount from when a signal is inputted to when the signal is outputted can be set in a wide range, while suppressing the circuit scale.
REFERENCES:
patent: 6449727 (2002-09-01), Toda
patent: 6549047 (2003-04-01), Yamazaki et al.
patent: 6738918 (2004-05-01), Toda
patent: 7102958 (2006-09-01), Lee et al.
patent: 7116146 (2006-10-01), Tokuhiro
patent: 7277356 (2007-10-01), Lee et al.
patent: 7298192 (2007-11-01), Tokuhiro
patent: 7369445 (2008-05-01), Lee et al.
patent: 7457174 (2008-11-01), Braun et al.
patent: 7457189 (2008-11-01), Lee et al.
patent: 7636273 (2009-12-01), Lee et al.
patent: 2002/0181639 (2002-12-01), Song
patent: 2003/0012320 (2003-01-01), Bell
patent: 2003/0041224 (2003-02-01), Toda
patent: 2005/0007835 (2005-01-01), Lee et al.
patent: 2005/0212574 (2005-09-01), Tokuhiro
patent: 2006/0161745 (2006-07-01), Lee et al.
patent: 2006/0262611 (2006-11-01), Lee et al.
patent: 2006/0290395 (2006-12-01), Tokuhiro
patent: 2007/0058478 (2007-03-01), Murayama
patent: 2007/0291575 (2007-12-01), Lee et al.
patent: 2008/0175071 (2008-07-01), Lee et al.
patent: 2009/0059680 (2009-03-01), Lee et al.
patent: 10 2005 021 894 (2006-01-01), None
patent: 1 047 220 (2000-10-01), None
patent: 11-316706 (1999-11-01), None
patent: 2004-531981 (2004-10-01), None
patent: 2005-286467 (2005-10-01), None
patent: 2005-322251 (2005-11-01), None
patent: 2007-72699 (2007-03-01), None
patent: WO 03/001732 (2003-01-01), None
Korean Office Action dated Dec. 17, 2009 and issued in corresponding Korean Patent Application 10-2008-0092358.
European Search Report issued Feb. 9, 2009 in corresponding European Patent Application 08163124.4.
“Chinese Office Action”, mailed by Chinese Patent Office and corresponding to Chinese application No. 200810149251.0 on Jul. 30, 2010, with English translation.
Fujitsu Limited
Fujitsu Patent Center
Hoang Huan
Lappas Jason
LandOfFree
Variable delay circuit, memory control circuit, delay amount... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Variable delay circuit, memory control circuit, delay amount..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable delay circuit, memory control circuit, delay amount... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2707820