Variable delay circuit for emulating word line delay

Details Variable delay circuit for emulating word line delay Variable delay circuit for emulating word line delay

1980-10-06

1984-01-10

Stellar, George G.

Static information storage and retrieval

Read/write circuit

Signals

328 56, 333138, 333164, G11C 700, H03H 730

Patent

active

044256337

ABSTRACT:
A semiconductor memory having an address buffer (10), row decoder (12), word lines (16), bit line (20) and sense amplifier (22) for accessing individual memory cells in an array of memory cells. In order to emulate worst case delays experienced in the word lines in accessing the last cells in the rows in order to prevent the sense amplifiers (22) from reading the bit lines (20) too soon, a tunable delay circuit (30) delays actuation of the sense amplifier. This circuit is divided into a plurality of impedance section with associated parasitic capacitance where groups of sections are bypassed by switching devices such as MOS transistors. The delay of a signal propagating through this tunable delay circuit can be varied by bypassing varying numbers of the sections with the switching devices.

REFERENCES:
patent: 3407392 (1968-10-01), Ishidate
patent: 3866061 (1975-02-01), Wen et al.
patent: 4162540 (1979-07-01), Ando
patent: 4231110 (1980-10-01), Stinehelfer

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