Variable data rate clock synthesizer

Details Variable data rate clock synthesizer Variable data rate clock synthesizer

1989-11-21

1991-05-21

Olms, Douglas W.

Pulse or digital communications

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331 14, 331 25, H03D 324

Patent

active

050181700

ABSTRACT:
A novel digital variable rate clock synthesizer is provided with a novel fractional-N digital phase locked loop. The all digital phase locked loop employs a digital input signal to a phase comparator which has a second input coupled to a digital control oscillator through a divide by N or a divide N+1 circuit. The digital output of the phase comparator is coupled to an error accumulating circuit which has a phase correction input signal from a fractional register and an associated accumulator. The output from the error accumulator is coupled to a pair of detectors for generating phase and frequency error detection signals which are digitally coupled to the control input of the digital control oscillator to provide a variable frequency output selected by the value of N and N+1.

REFERENCES:
patent: 4151485 (1979-04-01), LaFratta
patent: 4563657 (1986-01-01), Qureshi et al.
patent: 4568888 (1986-02-01), Kimura et al.
patent: 4574243 (1986-03-01), Levine
patent: 4791488 (1988-12-01), Fukazawa

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